Fully parallel fuzzy logic processor architecture: exceeding one billion rules per second

Michael Lees; Duncan Campbell

doi:10.1117/12.368442

8 October 1999 Fully parallel fuzzy logic processor architecture: exceeding one billion rules per second

Michael Lees, Duncan Campbell

Proceedings Volume 3893, Design, Characterization, and Packaging for MEMS and Microelectronics; (1999) https://doi.org/10.1117/12.368442
Event: Asia Pacific Symposium on Microelectronics and MEMS, 1999, Gold Coast, Australia

Abstract

A novel, very high-performance fuzzy logic processor architecture has been developed and conceptually proven. Processing of over 1.2 billion fuzzy logic instructions per second is possible. It is an 8-bit, fully parallel, synchronous, pipelined employing max-min based rule inferencing. The concept has been proven using complex programmable logic devices (CPLDs), exploiting both the high gate count and I/O pin count, as well as the reconfigurable structure. True non-singleton center-of-gravity defuzzification has also been developed incorporating an optimized dividing speeds significantly greater than the currently available commercial deices. Implementation in CPLDs allows reconfigurability in the fuzzy logic design, while custom devices allow a much greater degree of integration and potential for even greater processing speeds. High speed fuzzy logic processing is particularly suited to high bandwidth data processing applications such as virtual reality.

Citation Download Citation

Michael Lees and Duncan Campbell "Fully parallel fuzzy logic processor architecture: exceeding one billion rules per second", Proc. SPIE 3893, Design, Characterization, and Packaging for MEMS and Microelectronics, (8 October 1999); https://doi.org/10.1117/12.368442

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