3D packaging technology for vision CMOS VLSI: review and performance evaluation

Amine Bermak; Abdesselam Bouzerdoum; Kamran Eshraghian

doi:10.1117/12.364446

29 September 1999 3D packaging technology for vision CMOS VLSI: review and performance evaluation

Amine Bermak, Abdesselam Bouzerdoum, Kamran Eshraghian

Proceedings Volume 3891, Electronics and Structures for MEMS; (1999) https://doi.org/10.1117/12.364446
Event: Asia Pacific Symposium on Microelectronics and MEMS, 1999, Gold Coast, Australia

Abstract

In many applications, such as multimedia and on-chip camera, there is a need for the production of low power, low weight and low cost integrated circuits. Several CMOS vision chips have been proposed in the literature. Some limitations of conventional 2D architectures are discussed and a new 3D generation of vision chips is presented and reviewed in this paper. As a result of this analysis, some conclusions on the advantages and limitations of 2D vision chips and the feasibility of the 3D approach are explored.

Citation Download Citation

Amine Bermak, Abdesselam Bouzerdoum, and Kamran Eshraghian "3D packaging technology for vision CMOS VLSI: review and performance evaluation", Proc. SPIE 3891, Electronics and Structures for MEMS, (29 September 1999); https://doi.org/10.1117/12.364446

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