Challenges of damascene etching for copper interconnect

Paul Kwok Keung Ho; Mei-Sheng Zhou; Subhash Gupta; Ramasamy Chockalingam; Jianxun Li; Ming Hui Fan

doi:10.1117/12.360584

11 August 1999 Challenges of damascene etching for copper interconnect

Paul Kwok Keung Ho, Mei-Sheng Zhou, Subhash Gupta, Ramasamy Chockalingam, Jianxun Li, Ming Hui Fan

Proceedings Volume 3883, Multilevel Interconnect Technology III; (1999) https://doi.org/10.1117/12.360584
Event: Microelectronic Manufacturing '99, 1999, Santa Clara, CA, United States

Abstract

Dual damascene patterning is essential for the integration of copper into a high performance interconnect, hence the etching process becomes the most important challenge. This paper described the work on the dual damascene etching. The three most common schemes for patterning the dual damascene structure are trench-first, via-first (also known as counter-bore) and self-aligned etchings. Although only self- aligned etching requires the insertion of a stop layer, the stop layer is crucial to all schemes for a better control of the etching uniformity. The impact of using a stop layer with every dual damascene scheme was investigated. Lithography plays an important role in damascene etching. The use of negative-tone photoresist for metal trench masking and the challenge of forming a residue-free damascene structure in the presence of a bottom anti- reflecting coating were discussed.

Citation Download Citation

Paul Kwok Keung Ho, Mei-Sheng Zhou, Subhash Gupta, Ramasamy Chockalingam, Jianxun Li, and Ming Hui Fan "Challenges of damascene etching for copper interconnect", Proc. SPIE 3883, Multilevel Interconnect Technology III, (11 August 1999); https://doi.org/10.1117/12.360584

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