Optical clock distribution for a more efficient use of DRAMs

Daniel Litaize; Marc P.Y. Desmulliez; Jacques H. Collet; P. Foulk

doi:10.1117/12.308931

22 May 1998 Optical clock distribution for a more efficient use of DRAMs

Daniel Litaize, Marc P.Y. Desmulliez, Jacques H. Collet, P. Foulk

Proceedings Volume 3490, Optics in Computing '98; (1998) https://doi.org/10.1117/12.308931
Event: Optics in Computing '98, 1998, Bruges, Belgium

Abstract

Memory interconnect has become increasingly important for the electronics community since memory access times have not kept pace with the increase in speed of the central processor. The gap in relative performance between processors and DRAM memories has grown unabated by 50% per year over the last five years. Although cache memory can partially hide the main memory access time, the main bottleneck at the memory level remains unaffected. DRAM is to stay as the main component for high-capacity memory but its cycle time is not likely to decrease by much due to the very nature of the storage process (capacitive charge/discharge). The parallelisation of DRAM chips has increased the aggregate bandwidth but the latency time of the first word reaching the memory has decreased only slowly. A common solution chosen by all memory manufacturers and computer designers has been to widen the bus between the core processor and the (cache) memory in order to satisfy the bandwidth exhibited by the processor I 1 1. This strategy might not be the most efficient one. To illustrate this statement, consider a block transfer of 512 bits, say, which corresponds to the transfer of a data block between a core processor and its cache memory. An hypothetical new technology allows us to trans!èr data at a high-bit rate such as 500 MHz or 10 GHz for example. In the case of a cache, the address of the requested block would have to be submitted to bus arbitration before being sent to memory. Table I shows this typical case-study for a bus arbitration of IOns, an address to be transferred to the memory of (N)=40 bits, a memory read (and write) time oi(RW)=4Ons and a data block transfer of(M)=512 bits.

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Daniel Litaize, Marc P.Y. Desmulliez, Jacques H. Collet, and P. Foulk "Optical clock distribution for a more efficient use of DRAMs", Proc. SPIE 3490, Optics in Computing '98, (22 May 1998); https://doi.org/10.1117/12.308931

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KEYWORDS

Clocks

Optical clocks

Electronics

Interfaces

Manufacturing

Logic

Multiplexers

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