Data-flow architecture for high-speed optical processors

Kipp Andon Bauchert; Steven A. Serati

doi:10.1117/12.304789

23 March 1998 Data-flow architecture for high-speed optical processors

Kipp Andon Bauchert, Steven A. Serati

Proceedings Volume 3386, Optical Pattern Recognition IX; (1998) https://doi.org/10.1117/12.304789
Event: Aerospace/Defense Sensing and Controls, 1998, Orlando, FL, United States

Abstract

For optical processor applications outside of laboratory experiments, it is desirable to streamline the data flow in order to obtain the highest possible throughput from the system. This paper presents the data flow architectures for two optical processors designed and built by Boulder Nonlinear Systems, as well as the processor designs and some experimental data.

Citation Download Citation

Kipp Andon Bauchert and Steven A. Serati "Data-flow architecture for high-speed optical processors", Proc. SPIE 3386, Optical Pattern Recognition IX, (23 March 1998); https://doi.org/10.1117/12.304789

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available