Practical approach to control the full-chip-level gate CD in DUV lithography

Chul-Hong Park; Yoo-Hyon Kim; Hoong-Joo Lee; Jeong-Taek Kong; Sang-Hoon Lee

doi:10.1117/12.310751

29 June 1998 Practical approach to control the full-chip-level gate CD in DUV lithography

Chul-Hong Park, Yoo-Hyon Kim, Hoong-Joo Lee, Jeong-Taek Kong, Sang-Hoon Lee

Proceedings Volume 3334, Optical Microlithography XI; (1998) https://doi.org/10.1117/12.310751
Event: 23rd Annual International Symposium on Microlithography, 1998, Santa Clara, CA, United States

Abstract

A practical method to control the full chip level gate CD of a logic device with a 0.28 micrometer minimum design rule in DUV lithography is evaluated using an automatic optical proximity correction (OPC) software with empirical modeling. The CD variation on a chip results from the proximity and uniformity CD errors. The proximity error occupying more than 40% of total CD variation is caused by the pattern geometry, resist process, and mask CD error. In this paper, the OPC has been applied to line width narrowing and line-end shortening. The line-end shortening has been corrected by only the line- end extension instead of adding serifs which can be mistaken for defects during mask inspection. From this work, 43% reduction of the CD variation induced by proximity in the 3(sigma) standard deviation has been achieved at the 14 nm correction unit. Furthermore, the focus margin of 1.2 micrometer after OPC has been guaranteed. The results of line- end correction show that the line-end extension correction is sufficient to correct the overlap mismatching between the active and gate layers.

Citation Download Citation

Chul-Hong Park, Yoo-Hyon Kim, Hoong-Joo Lee, Jeong-Taek Kong, and Sang-Hoon Lee "Practical approach to control the full-chip-level gate CD in DUV lithography", Proc. SPIE 3334, Optical Microlithography XI, (29 June 1998); https://doi.org/10.1117/12.310751

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