In-line charge-trapping characterization of dielectrics for sub-0.5-um CMOS technologies

Pradip K. Roy; Carlos M. Chacon; Yi Ma; Gregory Horner

doi:10.1117/12.284669

2 September 1997 In-line charge-trapping characterization of dielectrics for sub-0.5-um CMOS technologies

Pradip K. Roy, Carlos M. Chacon, Yi Ma, Gregory Horner

Proceedings Volume 3215, In-Line Characterization Techniques for Performance and Yield Enhancement in Microelectronic Manufacturing; (1997) https://doi.org/10.1117/12.284669
Event: Microelectronic Manufacturing, 1997, Austin, TX, United States

Abstract

The advent of ultra-large and giga-scale-integration (ULSI/GSI) has placed considerable emphasis on the development of new gate oxides and interlevel dielectrics capable of meeting strict performance and reliability requirements. The costs and demands associated with ULSI fabrication have in turn fueled the need for cost-effective, rapid and accurate in-line characterization techniques for evaluating dielectric quality. The use of non-contact surface photovoltage characterization techniques provides cost-effective rapid feedback on dielectric quality, reducing costs through the reutilization of control wafers and the elimination of processing time. This technology has been applied to characterize most of the relevant C-V parameters, including flatband voltage (V_fb), density of interface traps (D_it), mobile charge density (Q_m), oxide thickness (T_ox), oxide resistivity (p_ox) and total charge (Q_tot) for gate and interlevel (ILO) oxides. A novel method of measuring tunneling voltage by this technique on various gate oxides is discussed. For ILO, PECVD and high density plasma dielectrics, surface voltage maps are also presented. Measurements of near-surface silicon quality are described, including minority carrier generation lifetime, and examples of their application in diagnosing manufacturing problems.

Citation Download Citation

Pradip K. Roy, Carlos M. Chacon, Yi Ma, and Gregory Horner "In-line charge-trapping characterization of dielectrics for sub-0.5-um CMOS technologies", Proc. SPIE 3215, In-Line Characterization Techniques for Performance and Yield Enhancement in Microelectronic Manufacturing, (2 September 1997); https://doi.org/10.1117/12.284669

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