Optimization of pre-gate clean technology for a 0.35-um dual-oxide/dual-voltage CMOS process

Hunter B. Brugge; Martin P. Karnett; Emmanuel de Muizon; Jingrong Zhou; Allen Page; Landon B. Vines; Bradley J. Haby

doi:10.1117/12.284619

27 August 1997 Optimization of pre-gate clean technology for a 0.35-μm dual-oxide/dual-voltage CMOS process

Hunter B. Brugge, Martin P. Karnett, Emmanuel de Muizon, Jingrong Zhou, Allen Page, Landon B. Vines, Bradley J. Haby

Proceedings Volume 3212, Microelectronic Device Technology; (1997) https://doi.org/10.1117/12.284619
Event: Microelectronic Manufacturing, 1997, Austin, TX, United States

Abstract

As voltages scale with device miniaturization, it is desirable to maintain dual-voltage operation for efficient system integration. While this dual-voltage approach is commonly used for CMOS EEPROM circuits, its use in an ASIC environment is relatively new. The effects of pre-gate clean processing technology on oxide integrity were investigated for both low (3.3 V) and high (5 V) voltage gate oxides in a 0.35 micrometer triple level metal CMOS process with dual gate oxide. Significant improvements in the high-voltage gate oxide quality were realized by reducing the temperature of the pre- gate SC1 (NH₄OH/H₂O₂/H₂O) cleaning solution and by minimizing the exposure time of the high-voltage gate oxide to HF. Also, addition of HCl to dilute HF as the final step in the pre-gate cleaning improved the high-voltage gate oxide quality. These improvements to the high-voltage gate oxide quality were achieved without compromising the quality of the low-voltage gate oxide.

Citation Download Citation

Hunter B. Brugge, Martin P. Karnett, Emmanuel de Muizon, Jingrong Zhou, Allen Page, Landon B. Vines, and Bradley J. Haby "Optimization of pre-gate clean technology for a 0.35-μm dual-oxide/dual-voltage CMOS process", Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); https://doi.org/10.1117/12.284619

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