Inter- and intra-die polysilicon critical dimension variation

Brian Stine; Duane S. Boning; James E. Chung; David A. Bell; Edward Equi

doi:10.1117/12.250826

12 September 1996 Inter- and intra-die polysilicon critical dimension variation

Brian Stine, Duane S. Boning, James E. Chung, David A. Bell, Edward Equi

Proceedings Volume 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II; (1996) https://doi.org/10.1117/12.250826
Event: Microelectronic Manufacturing 1996, 1996, Austin, TX, United States

Abstract

A methodology has been developed as part of a statistical metrology framework (1) to assess the relative range and distribution of intra-die, or die-level, polysilicon critical dimension variation as opposed to wafer-level, or inter-die, poly-CD variation; (2) to identify the key layout factors involved in poly-CD intra-die variation; and (3) to develop first-order semi-empirical models for poly-CD variation. A new approach utilizing multivariate analysis of variance methods is described to model the die- and wafer- level variation components. We show that pattern dependent variation is approximately twice as large as wafer-level variation. In addition, we find that spatial position plays a strong role: the first-order pattern dependent variation model (or die 'signature') shows a strong dependence on spatial position across the wafer, and individual components of the model demonstrate different spatial position sensitivities.

Citation Download Citation

Brian Stine, Duane S. Boning, James E. Chung, David A. Bell, and Edward Equi "Inter- and intra-die polysilicon critical dimension variation", Proc. SPIE 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II, (12 September 1996); https://doi.org/10.1117/12.250826

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