Patterning ULSI Circuits

John R. Carruthers

doi:10.1117/12.241809

14 June 1996 Patterning ULSI Circuits

John R. Carruthers

Proceedings Volume 2724, Advances in Resist Technology and Processing XIII; (1996) https://doi.org/10.1117/12.241809
Event: SPIE's 1996 International Symposium on Microlithography, 1996, Santa Clara, CA, United States

Abstract

The traditional scaling of feature sized to ever smaller dimensions which has driven the semiconductor industry for 30 years is being challenged by physical and cost limits. As we approach the development of the 180-nm generation, we have a quite different technology scenario facing us than we have seen in the past. The approaches being contemplated can be summarized in order of utility as (1) extensions of existing patterning methods, (2) nonlithography patterning approaches, (3) extensions of the optical projection/reduction approach, (4) new beam techniques, and (5) probe techniques. I will review the challenges in each of these categories and indicate where serious development efforts are needed to sustain technology scaling into the ULSI generations.

Citation Download Citation

John R. Carruthers "Patterning ULSI Circuits", Proc. SPIE 2724, Advances in Resist Technology and Processing XIII, (14 June 1996); https://doi.org/10.1117/12.241809

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