Application of SR lithography to 0.14-um device fabrication

Hiroaki Sumitani; Kenji Itoga; Hiroki Shimano; Sunao Aya; Hideki Yabe; Takashi Hifumi; Hiroshi Watanabe; Koji Kise; Masami Inoue; Kenji Marumoto; Yasutaka Nishioka; Haruhiko Abe; Nobutoshi Mizusawa; Kenji Saitoh; Yasuaki Fukuda; Shunichi Uzawa

doi:10.1117/12.240474

27 May 1996 Application of SR lithography to 0.14-um device fabrication

Hiroaki Sumitani, Kenji Itoga, Hiroki Shimano, Sunao Aya, Hideki Yabe, Takashi Hifumi, Hiroshi Watanabe, Koji Kise, Masami Inoue, Kenji Marumoto, Yasutaka Nishioka, Haruhiko Abe, Nobutoshi Mizusawa, Kenji Saitoh, Yasuaki Fukuda, Shunichi Uzawa

Author Affiliations +

Proceedings Volume 2723, Electron-Beam, X-Ray, EUV, and Ion-Beam Submicrometer Lithographies for Manufacturing VI; (1996) https://doi.org/10.1117/12.240474
Event: SPIE's 1996 International Symposium on Microlithography, 1996, Santa Clara, CA, United States

Abstract

The applicability of synchrotron radiation (SR) lithography to fabricate a giga bit scale dynamic random access memory (DRAM) cell array structure with minimum feature size of 0.14micrometers is demonstrated. Four lithography levels, isolation, transfer gate, bit line and storage node, were exposed by SR lithography. Exposure was carried out at Mitsubishi SR lithography facility using Canon x-ray stepper XFPA with a new negative tone resist and home-made x-ray mask set for each exposure level. These masks were composed of 2micrometers SiC membrane and 0.5micrometers W-Ti absorber. To minimize the mask-induced distortion, we applied the various techniques to the x-ray mask fabrication, changing the mask fabrication process flow, step annealing and electron beam multiple writing, and as the result, the pattern placement accuracy between two exposure level masks was about 50nm. Exposure latitude was about 22 percent for 0.15micrometers line and space pattern at the proximity gap of 30micrometers , and the critical dimension deviation for 0.14micrometers transfer gate pattern was 0.014micrometers at the almost same position in the mask in spite of the replication on the real DRAM topographic structure. The overlay accuracy was about 80nm for 20 X 20mm2 area. These results show SR lithography is the promising technique for giga bit level device fabrication.

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Hiroaki Sumitani, Kenji Itoga, Hiroki Shimano, Sunao Aya, Hideki Yabe, Takashi Hifumi, Hiroshi Watanabe, Koji Kise, Masami Inoue, Kenji Marumoto, Yasutaka Nishioka, Haruhiko Abe, Nobutoshi Mizusawa, Kenji Saitoh, Yasuaki Fukuda, and Shunichi Uzawa "Application of SR lithography to 0.14-um device fabrication", Proc. SPIE 2723, Electron-Beam, X-Ray, EUV, and Ion-Beam Submicrometer Lithographies for Manufacturing VI, (27 May 1996); https://doi.org/10.1117/12.240474

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