Statistical threshold-voltage variation and its impact on supply-voltage scaling

David Burnett; Shih-Wei Sun

doi:10.1117/12.221151

15 September 1995 Statistical threshold-voltage variation and its impact on supply-voltage scaling

David Burnett, Shih-Wei Sun

Proceedings Volume 2636, Microelectronic Device and Multilevel Interconnection Technology; (1995) https://doi.org/10.1117/12.221151
Event: Microelectronic Manufacturing '95, 1995, Austin, TX, United States

Abstract

A fundamental limit to the scaling of CMOS supply voltages (V_CC) exists due to the statistical variation of MOSFET threshold voltage (V_T). At the microscopic (device-to-device) level, an inherent variability in V_T exists due to the randomness of the number of dopants in the depletion region of the MOSFET. As the number of dopants in the depletion region decreases with scaling, the V_T variations will increase and become more significant. In addition to this fundamental variation in V_T, systematic V_T variations exist due to manufacturing fluctuations with the gate length, gate oxide thickness, implant uniformity, and anneal temperatures. For SRAM circuits, the V_T mismatch caused by channel dopant fluctuations degrades the cell stability and limits the minimum operating voltage of the SRAM. For logic circuits, the systematic V_T variations across a waver significantly increase the variation of the measured propagation delay on a wafer as V_CC is scaled down towards the MOSFET V_T. These limitations on V_CC scaling pose additional challenges in the design and manufacturing of devices and circuits for low-power systems.

Citation Download Citation

David Burnett and Shih-Wei Sun "Statistical threshold-voltage variation and its impact on supply-voltage scaling", Proc. SPIE 2636, Microelectronic Device and Multilevel Interconnection Technology, (15 September 1995); https://doi.org/10.1117/12.221151

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