Design and characterization of a 20 Gbit/s clock recovery circuit

Paulo M.P. Monteiro; J. Nuno Matos; Atilio M. S. Gameiro; Jose Ferreira da Rocha

doi:10.1117/12.201959

22 February 1995 Design and characterization of a 20 Gbit/s clock recovery circuit

Paulo M.P. Monteiro, J. Nuno Matos, Atilio M. S. Gameiro, Jose Ferreira da Rocha

Author Affiliations +

Proceedings Volume 2449, Fiber Optic Network Components; (1995) https://doi.org/10.1117/12.201959
Event: Advanced Networks and Services, 1995, Amsterdam, Netherlands

Abstract

In this communication we report the design of a clock recovery circuit produced for the 20 Gbit/s demonstrator of the RACE 2011 project `TRAVEL' of the European Community. The clock recovery circuit is based on an open loop structure using a dielectric resonator narrow bandpass filter with a high quality factor. A detailed electrical characterization of the circuit and also its sensitivity to temperature and detuning variations are presented. The experimental results show that the circuit is a very attractive solution for the forthcoming STM-128 optical links.

Citation Download Citation

Paulo M.P. Monteiro, J. Nuno Matos, Atilio M. S. Gameiro, and Jose Ferreira da Rocha "Design and characterization of a 20 Gbit/s clock recovery circuit", Proc. SPIE 2449, Fiber Optic Network Components, (22 February 1995); https://doi.org/10.1117/12.201959

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