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1 May 1994 16 MB DRAM trench depth characterization using dome scatterometry
Ziad R. Hatab, Steven L. Prins, John Robert McNeil, S. Sohail H. Naqvi
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Proceedings Volume 2196, Integrated Circuit Metrology, Inspection, and Process Control VIII; (1994) https://doi.org/10.1117/12.174118
Event: SPIE's 1994 Symposium on Microlithography, 1994, San Jose, CA, United States
Abstract
Advances in memory IC technology for dynamic random access memory (DRAM) devices have been achieved by increasing the number of memory cells occupying a certain chip area, consequently increasing memory size. Current methods of implementation include vertical topography, which relies on reducing the cell's thickness while increasing its depth in order to maintain the same capacitance of stored electrical charges. As the memory size on DRAM devices rises, memory cells have to reach deeper levels, thus making the process of measuring depth even harder. A novel metrology technique, which utilizes both 2-D diffraction analysis and multivariate statistical methods to measure deep trench depth, is discussed in this work. This technique was applied to two DRAM product wafers, and successful prediction of trench depth was obtained for both wafers with an accuracy of +/- 0.04 micrometers , or +/- 0.56% variation.
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Ziad R. Hatab, Steven L. Prins, John Robert McNeil, and S. Sohail H. Naqvi "16 MB DRAM trench depth characterization using dome scatterometry", Proc. SPIE 2196, Integrated Circuit Metrology, Inspection, and Process Control VIII, (1 May 1994); https://doi.org/10.1117/12.174118
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KEYWORDS
Scatterometry
Semiconducting wafers
Capacitance
Diffraction
Metrology
Statistical analysis
Statistical methods
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