ASIC implementation of recursive scaled discrete cosine transform algorithm

Bill N. On; Sam Narasimhan; Victor K.L. Huang

doi:10.1117/12.174963

2 May 1994 ASIC implementation of recursive scaled discrete cosine transform algorithm

Bill N. On, Sam Narasimhan, Victor K.L. Huang

Proceedings Volume 2187, Digital Video Compression on Personal Computers: Algorithms and Technologies; (1994) https://doi.org/10.1117/12.174963
Event: IS&T/SPIE 1994 International Symposium on Electronic Imaging: Science and Technology, 1994, San Jose, CA, United States

Abstract

A program to implement the Recursive Scaled Discrete Cosine Transform (DCT) algorithm as proposed by H. S. Hou has been undertaken at the Institute of Microelectronics. Implementation of the design was done using top-down design methodology with VHDL (VHSIC Hardware Description Language) for chip modeling. When the VHDL simulation has been satisfactorily completed, the design is synthesized into gates using a synthesis tool. The architecture of the design consists of two processing units together with a memory module for data storage and transpose. Each processing unit is composed of four pipelined stages which allow the internal clock to run at one-eighth (1/8) the speed of the pixel clock. Each stage operates on eight pixels in parallel. As the data flows through each stage, there are various adders and multipliers to transform them into the desired coefficients. The Scaled IDCT was implemented in a similar fashion with the adders and multipliers rearranged to perform the inverse DCT algorithm. The chip has been verified using Field Programmable Gate Array devices. The design is operational. The combination of fewer multiplications required and pipelined architecture give Hou's Recursive Scaled DCT good potential of achieving high performance at a low cost in using Very Large Scale Integration implementation.

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Bill N. On, Sam Narasimhan, and Victor K.L. Huang "ASIC implementation of recursive scaled discrete cosine transform algorithm", Proc. SPIE 2187, Digital Video Compression on Personal Computers: Algorithms and Technologies, (2 May 1994); https://doi.org/10.1117/12.174963

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KEYWORDS

Clocks

Field programmable gate arrays

Data storage

Video compression

Microelectronics

Very large scale integration

Video

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