Highly pipelined VLSI architecture for computation of fast Fourier transforms

Hong-Jin Yeh

doi:10.1117/12.160427

1 November 1993 Highly pipelined VLSI architecture for computation of fast Fourier transforms

Hong-Jin Yeh

Proceedings Volume 2027, Advanced Signal Processing Algorithms, Architectures, and Implementations IV; (1993) https://doi.org/10.1117/12.160427
Event: SPIE's 1993 International Symposium on Optics, Imaging, and Instrumentation, 1993, San Diego, CA, United States

Abstract

An on-chip VLSI architecture for computation of Fourier transforms is presented. It performs the arithmetic operations in a digit-level pipeline fashion. For this purpose, the implementation of arithmetic operators is based on on-line (i.e., digit-serial and most significant digit first) arithmetic, and the transforms are performed by a parallel-pipeline version of the Cooley- Tukey fast Fourier transform (FFT) algorithm.

Citation Download Citation

Hong-Jin Yeh "Highly pipelined VLSI architecture for computation of fast Fourier transforms", Proc. SPIE 2027, Advanced Signal Processing Algorithms, Architectures, and Implementations IV, (1 November 1993); https://doi.org/10.1117/12.160427

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