Hardware design of a fast neural network digital multiplier

Jayakuma Rudrupathy; Chia-Lun John Hu

doi:10.1117/12.140045

16 September 1992 Hardware design of a fast neural network digital multiplier

Jayakuma Rudrupathy, Chia-Lun John Hu

Proceedings Volume 1709, Applications of Artificial Neural Networks III; (1992) https://doi.org/10.1117/12.140045
Event: Aerospace Sensing, 1992, Orlando, FL, United States

Abstract

As reported previously, one can very efficiently convert an analog voltage to a clean M-valued digital number by using an M-zero neural network. Therefore, using these neural networks in conjunction with some analog arithmetic processors allows us to do the digital multiplication in a much more efficient way than the conventional binary multiplication. That is, we may have the advantages of the speed of the analog system and the accuracy of the M-valued digital system combined together in the new system. In this paper, we report the hardware design and the experimental result of the theoretical work that we previously published along this line.

Citation Download Citation

Jayakuma Rudrupathy and Chia-Lun John Hu "Hardware design of a fast neural network digital multiplier", Proc. SPIE 1709, Applications of Artificial Neural Networks III, (16 September 1992); https://doi.org/10.1117/12.140045

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