Paper
1 June 1992 Intermix technology: the key to optimal stepper productivity and cost efficiency
Mark A. Perkins, Jonathan M. Stamp
Author Affiliations +
Abstract
With device fabrication costs escalating dramatically each year and competition intensifying on a global level, chipmakers are seeking alternative equipment and fab designs to obtain an economic and technical edge. Nowhere is this more apparent than in the lithography area where equipment decisions greatly influence both the cost and performance of the production facility. This economic incentive has led to extensive use of intermix lithography. With this approach, less costly, more productive systems can be used to pattern the noncritical layers while saving the expensive, advanced performance tools for the critical levels. In the past, the majority of intermixing has occurred between steppers and projection aligners. However, due to increasingly complex device designs, intermix applications have expanded to include 1:1 steppers for noncritical levels, and reduction steppers for critical layers. The economic advantages inherent in this methodology are substantial. Productivity is increased and cost- per-wafer processed reduced for even the most sophisticated ICs. This paper will describe a lithographic intermix process for a high volume, l|im CMOS process using Ultratech 1:1 and Nikon 5:1 steppers.
© (1992) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Mark A. Perkins and Jonathan M. Stamp "Intermix technology: the key to optimal stepper productivity and cost efficiency", Proc. SPIE 1674, Optical/Laser Microlithography V, (1 June 1992); https://doi.org/10.1117/12.130352
Lens.org Logo
CITATIONS
Cited by 5 scholarly publications.
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Reticles

Optical lithography

Semiconducting wafers

Distortion

Lithography

Optical alignment

Visualization

RELATED CONTENT

Evaluation of the dual-exposure technique
Proceedings of SPIE (August 22 2001)
Mix And Match-10x Reduction Wafer Steppers
Proceedings of SPIE (September 13 1982)
Application Specific Wafer Stepper
Proceedings of SPIE (January 01 1987)
0.10-um overlay for DRAM production using step and scan
Proceedings of SPIE (June 01 1990)
Step and scan: the maturing technology
Proceedings of SPIE (May 26 1995)

Back to Top