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The paper is devoted to the design of the microarchitecture of a neural processor for hardware acceleration of CNN processing based on the author's architecture of processor. The paper presents various microarchitectural solutions that can be used to accelerate CNN processing. We explore methods to optimize hardware resources and reduce time required for CNN processing. To achieve high throughput in pipelined computation, different algorithms for convolution calculations in a systolic array are examined. Based on the results of this research, we provide estimates of the characteristics of the neural processor with the proposed microarchitecture. |
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