Research on dual stage pipeline MCU based on RISC-V on FPGA

Yujie Li; Zuo Qiao; Wei Liang; Lingjie Li; Haokang Zhang; Xiaodong Zhang; Chong Shen

doi:10.1117/12.3034759

11 July 2024 Research on dual stage pipeline MCU based on RISC-V on FPGA

Yujie Li, Zuo Qiao, Wei Liang, Lingjie Li, Haokang Zhang, Xiaodong Zhang, Chong Shen

Proceedings Volume 13210, Third International Symposium on Computer Applications and Information Systems (ISCAIS 2024); 1321032 (2024) https://doi.org/10.1117/12.3034759
Event: Third International Symposium on Computer Applications and Information Systems (ISCAIS 2023), 2024, Wuhan, China

Abstract

In response to the application requirements of low-power and high-performance MCU, this paper proposes a low-power microcontroller based on RISC-V instruction set and Dual stage pipeline architecture using a software hardware collaborative design method. It adopts a sequential Dual stage pipeline structure and supports configurable RV32I instruction set. The processor is designed using the comprehensible Verilog language and uses the ICB bus protocol as the interconnect bus to construct a System on Chip (SoC). In a simulation environment, the logic function of the microcontroller is verified by writing and inputting RV32I assembly instructions to test the program. After adding constraints under the Vivado synthesis tool, the processor RTL code is logically synthesized and the utilization of processor hardware resources is analyzed. Finally, the synthesized stream file is downloaded to the Artix7-100T FPGA chip development board. The verification results show that the designed microcontroller has correct logic function, uses low hardware overhead, and achieves relatively high performance indicators, which is suitable for high-performance with cost constraints Low power application areas.

(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

Yujie Li, Zuo Qiao, Wei Liang, Lingjie Li, Haokang Zhang, Xiaodong Zhang, and Chong Shen "Research on dual stage pipeline MCU based on RISC-V on FPGA", Proc. SPIE 13210, Third International Symposium on Computer Applications and Information Systems (ISCAIS 2024), 1321032 (11 July 2024); https://doi.org/10.1117/12.3034759

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