Micro-scale in-device overlay

Boris Habets; Stefan Eyring; Mirko Wittkoetter; Frank Laske; Marc Filzen; Clemens Utzny

doi:10.1117/12.3012648

9 April 2024 Micro-scale in-device overlay

Boris Habets, Stefan Eyring, Mirko Wittkoetter, Frank Laske, Marc Filzen, Clemens Utzny

Proceedings Volume 12955, Metrology, Inspection, and Process Control XXXVIII; 1295518 (2024) https://doi.org/10.1117/12.3012648
Event: SPIE Advanced Lithography + Patterning, 2024, San Jose, California, United States

Abstract

In device overlay is an important contributor to the on-product overlay budget. Well known are overlay bias effects, i.e., differences between overlay targets and in-product features. These can be corrected by a non-zero overlay correction in the run-to-run system. In this paper, we examine micro-scale effects, which happen on scales of a few micrometers, for which there is not exposure tool correction possible. With a high-voltage SEM, we use a novel method to investigate both logic and memory wafers and identify several micro-scale effects that are a significant contributor to the on-product overlay budget. We characterize the behavior across the wafer and local variations. In the root cause analysis, we find several possible explanations including mask writer issues, local stress, and impact of the product pitch.

Conference Presentation

(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

Boris Habets, Stefan Eyring, Mirko Wittkoetter, Frank Laske, Marc Filzen, and Clemens Utzny "Micro-scale in-device overlay", Proc. SPIE 12955, Metrology, Inspection, and Process Control XXXVIII, 1295518 (9 April 2024); https://doi.org/10.1117/12.3012648

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