A novel method for improving yield prediction by matching layout pattern and defect inspection

Min-Chul Han; Chang-Hun Ko; Cheol-Hwan Kim; Masayuki Terai; Hye-Sun Kim; Oh-Hun Kwon; Ji-Hyun Cheon; Jin-Woo Choi; Jung-Hoon Park; Kyu-Sul Park; Jae-Ho Pak; Do-Youn Park; Seung-Ryeol Oh; Min-Su Kim; Hyun-Woo Ryoo; Myung-Chul Shin; Bo-Tak Lim; Il-Mok Park; Hyuck-Joon Kwon; Yoon-Jong Song; Jung-Yun Choi; Gwan-Hyeob Koh; Hyung-Jong Ko; Yu-Gyun Shin

doi:10.1117/12.2656206

27 April 2023 A novel method for improving yield prediction by matching layout pattern and defect inspection

Min-Chul Han, Chang-Hun Ko, Cheol-Hwan Kim, Masayuki Terai, Hye-Sun Kim, Oh-Hun Kwon, Ji-Hyun Cheon, Jin-Woo Choi, Jung-Hoon Park, Kyu-Sul Park, Jae-Ho Pak, Do-Youn Park, Seung-Ryeol Oh, Min-Su Kim, Hyun-Woo Ryoo, Myung-Chul Shin, Bo-Tak Lim, Il-Mok Park, Hyuck-Joon Kwon, Yoon-Jong Song, Jung-Yun Choi, Gwan-Hyeob Koh, Hyung-Jong Ko, Yu-Gyun Shin

Author Affiliations +

Proceedings Volume 12496, Metrology, Inspection, and Process Control XXXVII; 124961N (2023) https://doi.org/10.1117/12.2656206
Event: SPIE Advanced Lithography + Patterning, 2023, San Jose, California, United States

Abstract

In order to minimize wafer loss and increase productivity, it is important to predict the wafer yield drop caused by defects in early manufacturing stage. In conventional yield prediction method, the chip failure was manually checked using images sampled by defect inspection. However, it is insufficient to predict yield accurately since the prediction was performed with only a few sampled defect images. Furthermore, the kill-ratio per defect was not estimated properly because the electrical properties were not considered in predicting a failure such as short or open. In this paper, we propose a new yield prediction method using defect and layout information with the following two characteristics. We tried to overcome the existing sampling limitations by using the defect inspection raw data that contains the coordinates and size information of all defects. In addition, we matched the electrical signal information of the layout pattern with silicon directly and then calculated the kill ratio per defect. The kill ratio per defect has doubled from 30% to 70% applied to sub-20nm Emerging memory devices. And we have confirmed that the yield prediction gap, which is the difference between the predicted yield and the actual yield, decreases from 31% to 8%. It is expected to reduce wafer loss about 10% in Emerging memory devices and same improvement will occur in other products such as DRAM, FLASH, and LOGIC devices by applying this sophisticated methodology.

Conference Presentation

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Min-Chul Han, Chang-Hun Ko, Cheol-Hwan Kim, Masayuki Terai, Hye-Sun Kim, Oh-Hun Kwon, Ji-Hyun Cheon, Jin-Woo Choi, Jung-Hoon Park, Kyu-Sul Park, Jae-Ho Pak, Do-Youn Park, Seung-Ryeol Oh, Min-Su Kim, Hyun-Woo Ryoo, Myung-Chul Shin, Bo-Tak Lim, Il-Mok Park, Hyuck-Joon Kwon, Yoon-Jong Song, Jung-Yun Choi, Gwan-Hyeob Koh, Hyung-Jong Ko, and Yu-Gyun Shin "A novel method for improving yield prediction by matching layout pattern and defect inspection", Proc. SPIE 12496, Metrology, Inspection, and Process Control XXXVII, 124961N (27 April 2023); https://doi.org/10.1117/12.2656206

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