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After large yield limiters are addressed during ramp, subtle layout pattern systematics continue to cause physical defects and prevent achieving entitlement throughout volume production of semiconductors. Current approaches are insufficient and require layout and location specific fallout information to further inform the pattern analysis engine. In this presentation we will describe a new approach to combine a pattern analysis engine (FIRE from PDF Solutions) with volume logic scan diagnosis (RCD from Siemens). The resulting yield Paretos include specific layout pattern systematic families as distinct root causes and show an overall increase in defect Pareto accuracy from ~70% to ~90%.
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Matthew Knowles, Jayant D'Souza, Manish Sharma, Hans Eisenmann, Thomas Zanon, "Novel approach to solving systematic pattern yield limiters with volume scan diagnosis," Proc. SPIE 12495, DTCO and Computational Patterning II, 1249513 (30 April 2023); https://doi.org/10.1117/12.2658022