A design of fetch target buffer implemented on XiangShan processor

Jiangrui Zou; Dan Tang; Ye Cai; Zusong Li

doi:10.1117/12.2642006

28 July 2022 A design of fetch target buffer implemented on XiangShan processor

Jiangrui Zou, Dan Tang, Ye Cai, Zusong Li

Proceedings Volume 12303, International Conference on Cloud Computing, Internet of Things, and Computer Applications (CICA 2022); 123032S (2022) https://doi.org/10.1117/12.2642006
Event: International Conference on Cloud Computing, Internet of Things, and Computer Applications, 2022, Luoyang, China

Abstract

In the design of modern high-performance processors, branch prediction is a very important component, and good branch prediction can greatly improve the performance of the processor. And Branch Target Buffer (BTB) is an important part of branch prediction. BTB is used to store information about branch instructions. Different from storing each branch as a unit, Glenn et al. proposed a BTB that stores branch information in a unit of fetch block, which they call Fetch Target Buffer (FTB). This design can optimize the timing by limiting the branch prediction width. But they did not give specific implementation details. In this paper, we propose a specific FTB implementation, and it is used in the second version architecture of XiangShan high-performance processor. First, we give the fields in the FTB entry in this design and their corresponding functions. Most BTB entries need to store the following information: branch tag, branch type, target address. In addition to these fields in this paper, FTB will also store other information for managing entries and optimizing branch prediction performance. Secondly, we proposed the management strategy of FTB entries, when to add, modify, and replace. After all the instructions in a fetch block are committed, we need to decide whether this fetch block needs to be written to FTB, and which way to write, how to avoid the problem of multiple hits. Under the 14nm process, compared to the 1.8GHz of the first version of the architecture, the frequency of the new architecture using FTB can be increased to 2GHz.

Citation Download Citation

Jiangrui Zou, Dan Tang, Ye Cai, and Zusong Li "A design of fetch target buffer implemented on XiangShan processor", Proc. SPIE 12303, International Conference on Cloud Computing, Internet of Things, and Computer Applications (CICA 2022), 123032S (28 July 2022); https://doi.org/10.1117/12.2642006

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