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PDF’s electrically testable structures, called Characterization Vehicles™ (CV’s), have been extremely successful in characterizing printability windows of the leading- edge technologies for the last 15 years. We have been able to demonstrate clear correlations between the electrical misalignment data and product yield for several technology generations and these CV’s have been employed in all leading foundries. However, their placement is limited to the scribe lines and in many fabs they are tested only at the end of wafer processing. We have conducted many experiments that demonstrated their accuracy vs. the cross-sectional TEM and concluded that the final edge placement error (EPE) does not always correlate to in-line overlay measurements, and often exceeds by far the allowable tolerances, leading to the product yield loss. With the multiple patterning schemes and recently EUV, there is a clear need to fully characterize the EPE budget in the technology development and, if this information is available in-line, use this information for process control by feeding it back to the scanners. Over the last 8 years a new technology called Design For Inspection™ (DFI) has been developed and already proven in all major foundries. Specially designed test structures are placed within the product die in place of the filler cells and dummy fill without any area penalty, as well as in the scribe lines, which allows for the EPE monitoring with sub-Design Rule designs. All DFI structures are tested with a custom (designed and manufactured by PDF) eBeam voltage contrast tool with a very high speed and sub-nm resolution for the EPE characterization. The new vector scan eProbe-250 tool is capable of testing billions of DFI structures sites with a speed up to 5 billion sites/hour on a single wafer. Contrary to the typical eBeam machines, it utilizes the gray scale data from the tool to allow for the marginality extraction (soft failures which may have significant reliability impact). This allows for extensive Design of Experiment (DoE) to be performed to fully characterize the EPE and other process marginalities. This DFI methodology has been enthusiastically received by not only foundries but also leading fabless companies and more than 20 tape-outs of MultiProduct Wafers (MPW’s) and actual product wafer scribes have been already executed proving the value of this methodology from the 14nm down to 5 nm nodes. This methodology has been currently applied to the EUV characterization where the overlay and local LER variations contribute the most to the EPE budget.
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