Design, patterning, and process integration overview for 2nm node

Syed Muhammad Yasser Sherazi; Yi-Han Chang; Youssef Drissi; Bilal Chehab; Jae Uk Lee; Victor Vega Gonzales; Ryan Ryoung Han Kim

doi:10.1117/12.2615311

26 May 2022 Design, patterning, and process integration overview for 2nm node

Syed Muhammad Yasser Sherazi, Yi-Han Chang, Youssef Drissi, Bilal Chehab, Jae Uk Lee, Victor Vega Gonzales, Ryan Ryoung Han Kim

Author Affiliations +

Proceedings Volume 12052, DTCO and Computational Patterning; 120520F (2022) https://doi.org/10.1117/12.2615311
Event: SPIE Advanced Lithography + Patterning, 2022, San Jose, California, United States

Abstract

According to the Power-Performance-Area requirements in advanced technology node, we already scaled down poly pitch (CPP) and metal pitch (MP) which considered as main factors to form standard cell (SDC) area. However, in recent technology nodes, the scaling of CPP and MP started to slow down, due to the physical limitation. To continue to meet the requirements, combined with Design-Technology co-optimization (DTCO), the height of standard cell would become the main factor here, which we could reduce it by reducing the number of tracks. In this paper, we would introduce 3DIC as one of the design options for 2nm node to keep scaling by reducing the cell height with its specific 3D structure and inserted booster. Also, we would introduce the coming challenges as importing 3D-IC to 2nm technology node.

Conference Presentation

Citation Download Citation

Syed Muhammad Yasser Sherazi, Yi-Han Chang, Youssef Drissi, Bilal Chehab, Jae Uk Lee, Victor Vega Gonzales, and Ryan Ryoung Han Kim "Design, patterning, and process integration overview for 2nm node", Proc. SPIE 12052, DTCO and Computational Patterning, 120520F (26 May 2022); https://doi.org/10.1117/12.2615311

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