Presentation + Paper
17 November 2021 Exploring the stochastics cliff: understanding the impact of LER/LWR to stochastic defectivity and yield
Author Affiliations +
Abstract
Extreme ultraviolet lithography (EUV) materials and processes are constantly evolving and maturing, making sub-30 nm pitch single-exposure yield feasible. Characterization methodologies for stochastic variations are well-documented at this stage, with most employing critical dimension scanning electron microscopy (CDSEM) and a form of defect inspection to quantify line edge roughness (LER), local critical dimension uniformity and patterning failures. In this paper, the link between LER and stochastic defectivity is explored at a deeper level, as we probe the possibility of nucleating stochastic failures with programmed LER structures at 30 nm pitch using CDSEM, optical inspection and electrical yield data. First, we characterize LER post-develop and post-etch using unbiased LER measurements. Second, we study the defectivity and optical characteristics of the programmed LER pattern post hard mask open using optical inspection. Specifically, we measure the optical noise induced by programmed LER, the inspection performance in terms of defect capture and nuisance rate, and the predictive capability of optical inspection through a comparison of defectivity with electrical yield data.
Conference Presentation
© (2021) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jennifer Church, Graham Jensen, Romain Lallement, Andrew Cross, and Luciana Meli "Exploring the stochastics cliff: understanding the impact of LER/LWR to stochastic defectivity and yield", Proc. SPIE 11854, International Conference on Extreme Ultraviolet Lithography 2021, 118540X (17 November 2021); https://doi.org/10.1117/12.2600877
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Line edge roughness

Stochastic processes

Inspection

Modulation

Critical dimension metrology

Semiconducting wafers

Defect inspection

Back to Top