Performance of stacked nanosheet gate all around FET’s with EUV patterned gate and sheets

Indira Seshadri; Jennifer Church; Prateek Hundekar; Mary Breton; Jingyun Zhang; Eric Miller; Andrew Greene; Julien Frougier; Chris Waskiewicz; Tao Li; Tsung-Sheng Kang; Daniel Dechene; Carl Radens; Stuart Sieg; Veeraraghavan Basker; Nelson Felix; Chris A. Mack

doi:10.1117/12.2583897

22 February 2021 Performance of stacked nanosheet gate all around FET’s with EUV patterned gate and sheets

Indira Seshadri, Jennifer Church, Prateek Hundekar, Mary Breton, Jingyun Zhang, Eric Miller, Andrew Greene, Julien Frougier, Chris Waskiewicz, Tao Li, Tsung-Sheng Kang, Daniel Dechene, Carl Radens, Stuart Sieg, Veeraraghavan Basker, Nelson Felix, Chris A. Mack

Author Affiliations +

Proceedings Volume 11609, Extreme Ultraviolet (EUV) Lithography XII; 116090S (2021) https://doi.org/10.1117/12.2583897
Event: SPIE Advanced Lithography, 2021, Online Only

Abstract

Gate all around stacked nanosheet FET’s have emerged as the next technology to FinFET’s for beyond 7-nm scaling. With EUV technology integrated into manufacturing at 7nm, there is great interest to enable EUV direct print patterning for nanosheet technology in the FEOL. While sheet and gate pitches expected for the beyond 7nm node fall within the EUV direct print regime (>40nm), it is unclear if direct print solutions can meet device performance requirements at technology critical sheet widths and gate lengths. Here, we demonstrate electrical performance of nanosheet FET’s with 20 – 80 nm wide sheets with 40-150 nm pitch gates patterned with single expose EUV. We compare results against a benchmark double patterning process towards meeting variability, device and critical dimension targets. We also explore the limits of process and material knobs - resists, illuminations and etch chemistries with the specific goal of reducing LER/LWR and towards shrink for further scaling. Our results demonstrate crossover points between direct print EUV and double patterning processes for nanosheet technology and identify relevant design guidelines and focus areas to successfully enable EUV for the FEOL in nanosheets.

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Indira Seshadri, Jennifer Church, Prateek Hundekar, Mary Breton, Jingyun Zhang, Eric Miller, Andrew Greene, Julien Frougier, Chris Waskiewicz, Tao Li, Tsung-Sheng Kang, Daniel Dechene, Carl Radens, Stuart Sieg, Veeraraghavan Basker, Nelson Felix, and Chris A. Mack "Performance of stacked nanosheet gate all around FET’s with EUV patterned gate and sheets", Proc. SPIE 11609, Extreme Ultraviolet (EUV) Lithography XII, 116090S (22 February 2021); https://doi.org/10.1117/12.2583897

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