The first CMOS approach was to carry the TDI functionality using digital summation. This approach quickly demonstrated limitations in terms of line rate and power consumption as the entire sensor has to be read for every line on the ground that is sampled. More recently CMOS technology has matured the charge domain CCD approach with comparable electro-optical performance to CCDs while offering higher speed, smaller pixel pitch and high level of integration. This latest technology step has also considerably eased the integration of the sensor into the satellite, opening new opportunities to produce focal planes at significantly lower cost with much reduced power dissipation, size and weight. The challenge has been to establish a CCD on CMOS technology that can obtain a similar full well capacity and charge transfer efficiency (CTE) performance to CCDs. This CCD on CMOS technology has now reached the point where the performance is comparable to CCDs but with very much lower operating voltages. This paper will present the evolution of earth scanning image sensors with a focus on the latest TDI CMOS technology including the recent results obtained with the latest CMOS technology using TDI in charge domain approach. These results will include FWC, CTE, radiation performance as well as results from very high speed, up to 3.6Gbps output stream, and highly integrated readout circuitry. Finally we will provide details of new devices that will provide performance that would not have been possible with CCDs. |
2.CCD STRUCTUREThe pixel architecture used for TDI-CMOS charge domain (or qTDI) is represented in Figure 1. It is a 4 phase CCD structure with minimum poly-poly gap (0.25μm). The pixel is bi-directional with identical output ports at either end of the CCD structure. This structure is based on a buried channel implantation to achieve good charge transfer efficiency (CTE) and to minimize post radiation degradation as seen with surface channel approach [1]. The clocking of the CCD phases is overlapping as shown in Figure 2. The transfer direction can simply be changed by swapping two of the clocks. This feature is accessible via an SPI interface. Gate voltage and clock slew rate are optimized for best full well capacity and CTE trade-off. The clock generator and drivers are embedded in the chip greatly simplifying the integration of this detector. Note that careful lay out technics are used to obtain correct clock slew rate and avoid IR drops due to current demand during switching activity. 3.PROTOTYPE EVALUATIONA prototype, see Figure 3, was developed to test CCD structure variants with 2 pixel pitches of 5 and 10 μm. This prototype was designed to not only prove the pixel technology but also a periphery to support high line rate up to 300klines/s. The image area is composed of a single TDI-CCD structure of 4096 columns with 256 or 64 TDI stages depending on the pixel pitch. In order to achieve this line rate of up to 300 klines/s a very fast single slope 12 bits ADC technique has been developed and implemented. The 12 bits conversion is achieved in 0.9μs. The classic single slope ADC architecture was modified to work around a counter generating eleven Gray code bits and three phase-shifted clocks providing 12 bits output (see Figure 4) in total at very high line rates:
The complete column readout path is illustrated in Figure 5. The data resulting of the image conversion is then sent to a gigabit transmitter (GTX) composed of a serializer working in double data rate mode (DDR) at 3.6GHz and a CML (3.6Gb/s) data driver. A high speed CML output driver has been selected to minimize the number of output ports to simplify the interface to the data capturing device. Input signals such as clock, integration control and SPI interface use LVDS format. The CCD-structure clock drivers require attention and floor planning, see Figure 6: 4.PROTOTYPE DEVICE EXPERIMENTAL RESULTS4.1Results summaryTable 1 summarizes the obtained results. The results demonstrate good performance and readiness for use for space mission. Table 1:Prototype summary results.
4.2Electro-optical performanceThe implementation of good CCD structure in CMOS represents several challenges of which the two mains ones are obtaining good CTE and high enough full well capacity. In that respect and compared to CCD the limitations of CMOS technology to be overcome are non-overlapping poly gates and lower supply voltages. The former affects the CTE and the later the FWC. In addition and similar to CCD technology a surface channel CCD structure although giving higher full well will suffer from high CTE degradation end of life (EOL) worsening drastically MTF performance. This is because trap generated at the silicon surface will trap and release electron at different clock phases. Hence all the CCD structure pixels use buried channel architecture despite the loss of Full Well. An advantage of the buried implant is that it reduces the potential pockets of poly-poly gap (0.25μm). In order to overcome the lower supply voltage of CMOS technology negative supplies are used to increase the potential across each pixel. It can be noted that summing in the digital domain two of the CCD structure, also called sub-TDI arrays is recommended to increase the signal noise ratio. This is because while the total charge is added in a linear fashion the noise is added in root square fashion only. A summary of the main results are given below and can be found in more details in [1]. On a 5μm pitch CCD structure with anti-blooming a FWC of 30ke- was measured with a CTE better than 0.99999. The signal non-linearity achieved is less than 2%, while the dark current performance is 3.7 nA/cm2 with a temperature doubling factor of 9.5°C. The Arrhenius plot indicates an activation energy (Ea) of 0.6eV. This corresponds to half the silicon band gap confirming that the dark current source is the conventional Shockley-Read-Hall (SRH) mechanism. The charge conversion efficiency graph shows a pixel conversion gain of 35μV/e-. This gain is designed to optimise noise floor versus full well and hence dynamic range. 4.3RadiationThe radiation immunity or degradation model is a key aspect of validation of a new technology. In the context of the qTDI detector two aspects matters: the CCD structure behaviour with Gamma and Proton and the readout periphery immunity to Heavy Ion. Results obtained on these two aspects are shown below. 4.4CCD structureFor the CCD structure the concerns are mainly around two parameters, dark current (including bright pixel) and CTE performance degradation when subject to Gamma and proton radiation. The results [4] below show a good behaviour with acceptable results for a flight mission. The Gamma radiation increased the dark signal of the Non-Anti-bloomed (AB) split by a factor 2 at 30krad while the AB split was more affected (x2.5). This is explained by the fact that AB split has less STI and less active area but has more gate edges and poly gaps (Non-continuous poly gates). A similar observation is made after the proton irradiation, see table for details. The higher increase for the AB splits is also explained by the higher level of gate edges. Table 2Dark current summary at 30krad and 5x1010 p/cm2 Proton exposure.
The results below show a very small and similar CTE degradation of both the AB and non-AB versions of the prototype device with Gamma and proton up to doses that would be expected in typical space based applications Single Event Effect (SEE)Usually, the SEE is categorized in:
Teledyne has developed design rules and layout rules that have secured several projects such as MTG or METImage giving high immunity to heavy ion. These results have been reported in details at the ICSO conference 2016 and below is a summary table. Table 3MTG-FCI results 3.
5.NEXT ACTIVITIESThe technology described in this paper is now being used to make a prototype full sized TDI CMOS image sensor called the CIS125 in a program funded by the UK Space Agency (CEOI). The architecture developed is shown Figure 11. This qTDI detector is composed of 4 panchromatic (PAN) bands and 8 multi-spectral (MS) bands. The configuration reported here is optimised for the CEOI program and each PAN and MS are composed of sub-TDI bands (A&B) that enhance the full well by adding digital summation to the charge domain performance. The PAN and MS number of TDI lines were carefully chosen to optimise application needs versus silicon area. Each sub-TDI needs to be read out separately and therefore needs its own conversion. This is the equivalent of reading out 16 independent bands. This sensor is a stitched device of 16k columns for the PAN and 8k columns for the MS. The pixel is 5μm and 10μm for the PAN and MS respectively, see Table 4. The high speed ADC per column described earlier allows a line rate of up to 14kHz if all of the sensor lines and sub lines are read. A single read path is shared between all bands enabling the implementation of a maximum number of bands without the need of 2D stitching technology and optimising power consumption. Table 4Configuration for CEOI program.
The number of TDI stages per bands are selectable as follow:
This sensor will be made with a 0.18μm Imaging CMOS process using thick and high resistivity epitaxial silicon. The device is also back-illuminated to improve fill factor and it will be thinned (using Teledyne-e2v process) to optimise QE versus MTF. To enhance further it performance an Anti-reflection coating will be deposited as well as black-coating between channels to avoid straight light effects. CIS125 is designed as a modular platform to enable to adapt to a wide range of configuration with lower risk associated to new development. 6.SUMMARYA TDI-CMOS sensor for high resolution earth observation has been presented:
In this paper has also presented the performance of the CCD structure used and demonstrated high TRL level:
This technology has now reached a maturity where full sensors are being design for flight applications and example is give showing the type of architecture that is possible in a full sensor design 7.7.ReferencesHyun Jung, Lee,
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