Wafer Inspection Technology For Submicron Devices

Kazunori Okamoto; Shokichi Yoshitome

doi:10.1117/12.953127

19 July 1989 Wafer Inspection Technology For Submicron Devices

Kazunori Okamoto, Shokichi Yoshitome

Proceedings Volume 1087, Integrated Circuit Metrology, Inspection, and Process Control III; (1989) https://doi.org/10.1117/12.953127
Event: 1989 Santa Clara Symposium on Microlithography, 1989, San Jose, CA, United States

Abstract

As processes advance into production of submicron devices, reducing defect density to an acceptable level is becoming a more difficult task. To deal with this problem, new wafer inspection technologies have been developed. The new systems can inspect dense patterned wafers to identify particles and process defects. An improvement over manual inspection is realized in defect sensitivity, inspection speed, and consistency of results. The technologies available for automatic wafer inspection have different capabilities. Therefore, to take advantage of each technology, the methods for system utilization must be considered. The methods involve identification of killer defects and determining the problem cause and required corrective action. This paper will focus on typical defects found in a submicron manufacturing facility. An evaluation of new wafer inspection technology will be described. Examples will be given to illustrate how inspection technology can be applied to solve problems in a production line.

Citation Download Citation

Kazunori Okamoto and Shokichi Yoshitome "Wafer Inspection Technology For Submicron Devices", Proc. SPIE 1087, Integrated Circuit Metrology, Inspection, and Process Control III, (19 July 1989); https://doi.org/10.1117/12.953127

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