|
Photonic integrated circuits (PICs) have been demonstrated as a promising technology to implement flexible and hitless reconfigurable devices for telecom, datacom and optical interconnect applications. However, the complexity scaling of such devices is raising novel needs related to their control systems, and the automatic calibration, reconfiguration and operation of these complex architectures both during manufacturing and in service is still an open issue.
In this contribution, we report our recent achievements on the automatic hitless tuning of a telecommunication-graded filter operating in the L band, fabricated on a commercial foundry Silicon Photonics (SiP) run. A novel channel labeling strategy is used to automatically identify the desired channel within a Dense Wavelength Division Multiplexing (DWDM) through a FPGA-embedded closed-loop control algorithm.
The photonic architecture consists of a hitless third order Micro Ring Resonator (MRR) filter with 8 nm Free Spectral Range (FSR), integrating transparent detectors (ContactLess Integrated Photonic Probes - CLIPP) as power monitors and thermooptic actuators. Transparent detectors enable to control the input/output port of the filter without introducing any loss to the WDM channel comb. Hitless operation is achieved through a pair of switchable Mach-Zehnder interferometers used as input/output couplers of the MRR filter. The fabricated device has a 3 dB bandwidth of 40.7 GHz and provides a through-port in-band isolation of 23 dB and a drop port isolation of 25 dB at 50 GHz spacing from the dropped channel. Hitless reconfiguration is achieved with more than 30 dB isolation during channel selection.
The automatic tuning and locking technique is based on the use of a pilot tone generated locally at the node site and applied as a low frequency (few kHz), small modulation index (< 8%), amplitude modulation on the channel to be added to the network. The effectiveness and robustness of the automatic controller for tuning and stabilization of the filter is demonstrated by showing that no significant bit-error rate (BER) degradation is observed in an adjacent channel while the filter is being reconfigured. In addition, the convergence of the algorithm is shown to require only few tens of iterations, each one requiring a few milliseconds.
The FPGA-embedded control technique together with the compactness provided by SiP meets the integration requirements for high capacity networks and pluggable modules. In addition, the filter unit can be cascaded with other units to realize a multichannel reconfigurable add-drop architecture operating on several wavelengths at the same time with complete independency.
|
