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In processing a semiconductor product (from discrete devices up to the most complex products produced) we find more photolithographic steps in wafer fabrication than any other kind of process step. Thus, the success of a semiconductor manufacturer hinges on the optimization of their photolithographic processes. Yet, we find few companies that have taken the time to properly characterize this critical operation; they are sitting in the "passenger's seat", waiting to see what will come out, hoping that the yields will improve someday. There is no "black magic" involved in setting up a process at its optimum conditions (i.e. minimum sensitivity to all variables at the same time). This paper gives an example of a real world situation for optimizing a photolithographic process by the use of a properly designed experiment, followed by adequate multidimensional analysis of the data. Basic SPC practices like plotting control charts will not, by themselves, improve yields; the control charts are, however, among the necessary tools used in the determination of the process capability and in the formulation of the problems to be addressed. The example we shall consider is the twofold objective of shifting the process average, while tightening the variance, of polysilicon line widths. This goal was identified from a Pareto analysis of yield-limiting mechanisms, plus inspection of the control charts. A key issue in a characterization of this type of process is the number of interactions between variables; this example rules out two-level full factorial and three-level fractional factorial designs (which cannot detect all of the interactions). We arrive at an experiment with five factors at five levels each. A full factorial design for five factors at three levels would require 3125 wafers. Instead, we will use a design that allows us to run this experiment with only 25 wafers, for a significant reduction in time, materials and manufacturing interruption in order to complete the experiment. An optimum solution is then determined via response surface analysis and a series of 3-D and contour plots are shown. The offset between the mask dimensions and poly CD at the optimum operating conditions is discussed with respect to yield, profits and return-on-investment. The expert system used for process optimization covers all types of process steps, producing the best custom designed experiment based on the actual equipment used. The knowledge base contains parameter lists, by machine make and model, ranked by sensitivity and controllability. One option allows 3-D spatial characterization of equipment. For the purpose of this presentation, we will assume that we want to optimize a photo-lithographic process used for polysilicon pattern definition and that we have determined minimum and maximum line widths, based on electrical yield requirements of the product. For this MOS process, the minimum critical dimension (CD) for the poly gate was determined by punchthrough voltage, threshold voltage, etc., while the maximum CD was determined from other performance factors like access time. We will start with the product engineer's analysis.
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