Analysis Of Low-Level Computer Vision Algorithms For Implementation On A Very Large Scale Integrated (VLSI) Processor Array

Michael R. Lowry; Allan Miller

doi:10.1117/12.934096

23 May 1983 Analysis Of Low-Level Computer Vision Algorithms For Implementation On A Very Large Scale Integrated (VLSI) Processor Array

Michael R. Lowry, Allan Miller

Author Affiliations +

Proceedings Volume 0360, Robotics and Industrial Inspection; (1983) https://doi.org/10.1117/12.934096
Event: 26th Annual Technical Symposium, 1982, San Diego, United States

Abstract

In a recent paper [Lowry 81], we described an architecture for a computer vision rectangular processor array that is suitable for VLSI implementation. In this paper we will review that architecture and discuss extensions to it and present results of an array simulator applied to vision algorithms. We will also present an algorithm for re-routing an array with bad processors into a working subset of the array, making it feasible to implement a large array on one wafer-sized chip.

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Michael R. Lowry and Allan Miller "Analysis Of Low-Level Computer Vision Algorithms For Implementation On A Very Large Scale Integrated (VLSI) Processor Array", Proc. SPIE 0360, Robotics and Industrial Inspection, (23 May 1983); https://doi.org/10.1117/12.934096

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