This PDF file contains the front matter associated with SPIE Proceedings Volume 8628, including the Title Page, Copyright Information, Table of Contents, and the Conference Committee listing.

The current development in photonics for communications and interconnects pose increasing requirements on reduction of footprint, power dissipation and cost, as well as increased bandwidth. Integrated nanophotonics has been viewed as one solution to this, capitalizing on development in nanotechnology as such as well as on increased insights into light matter interaction on the nanoscale. The latter can be exemplified by plasmonics and low-dimensional semiconductors such as quantum dots (QDs). In this scenario the development of better electrooptic materials is also of great importance, the electrooptic polymers being an example, since they potentially offer improved properties for optical phase modulators in terms of power and probably cost and general flexibility. Phase modulators are essential for e.g. the rapidly developing advanced modulation formats for telecom, since phase modulation basically can generate any type of modulation. The electrooptic polymers, e.g. in combination with plasmonics nanoparticle array waveguides or nanostructured hybrid plasmonic media can theoretically give extremely compact and low power dissipation modulators, still to be demonstrated. The low-dimensional semiconductors, e.g. in the shape of QDs, can be employed for modulation or switching functions, offering possibilities in the future for scaling to 2 or 3 dimensions for advanced switching functions. In both the plasmonics and QD cases, nanosizing and low power dissipation are generally due to near-field interactions, albeit being of different physical origin in the two cases. A comparison of all-optical and electronically controlled switching is given.

Silicon (Si) photonic wire waveguides provide a compact photonic platform on which passive, dynamic, and active photonic devices can be integrated. This paper describe the demonstrations of several kinds of integrated photonic circuits. The platform consists of Si wire, silicon-rich Si dioxide (SiO_x) and Si oxinitride (SiON) waveguides for passive devices and a Si rib waveguide with a p-i-n structure and a germanium (Ge) device formed on Si slab for active devices. One of the key technologies for the photonic integration platform is low temperature fabrication because a back-end process with high temperature may damage active and electronic devices. To overcome this problem, we have developed electron cyclotron resonance chemical vapor deposition as a low-temperature deposition technique. Another key technology is polarization manipulation for reducing polarization dependence. A polarization diversity circuit is fabricated by applying Si wire and SiON integration. The polarization-dependent loss of the diversity circuit is less than 1 dB. Moreover we have developed several kinds of integrated circuit including passive, dynamic and active devices. Ge photodiodes are monolithically integrated with an SiO_x-arrayed waveguide grating (AWG). We have confirmed that the operation speed of the integrated Ge photodiode is over 22 Gbps for all 16 channels. Variable optical attenuators (VOAs) fabricated on the Si p-i-n rib waveguides and an AWG based on the SiO_x waveguide are integrated successfully. The total size of 16-ch-AWG-VOAs is 15 8 mm². The device has already been made polarization independent. Furthermore electronic circuits are successfully mounted on the integrated photonic device by using flip-chip bonding.

Various methods of hybrid integration of photonic circuits are discussed focusing on merits and challenges. Material platforms discussed in this report are mainly polymer and silica. We categorize the hybridization methods using silica and polymer waveguides into two types, chip-to-chip and on-chip integration. General reviews of these hybridization technologies from the past works are reviewed. An example for each method is discussed in details. We also discuss current status of our silica PLC hybrid integration technology.

Recently hybrid plasmonic waveguides have been proposed and attracted much attention as a good option to realize a nano-scale light confinement as well as a relatively long propagation distance. Furthermore, hybrid plasmonics waveguides offer a way to transfer and process both photonic and electronic signals along the same plasmonic circuit, which is desirable in order to combine the advantage of both photonics and electronics for high-speed signal processing and an easy realization of active components. In this paper, we give a review for our recent work on silicon hybrid nanoplasmonic waveguides and devices.

Silicon-on-insulator (SOI) is becoming an important technology platform in nanometer scale CMOS integrated circuits. The platform offers a number of distinct advantages over bulk CMOS for materializing silicon light sources based on hot carrier luminescence. This work describes the design of nanoscale silicon structures for enhanced light emission with improved power efficiency, which allows the use of SOI light sources in short-haul optical communication links with extended possibilities for other applications. It has been shown experimentally that reducing the dimensions of the active material results in an improvement of electroluminescent power emitted from forward-biased pn-junctions. Previously published results show a similar trend for light sources based on hot carrier luminescence. Building on our previous work in SOI light sources, multiple fingerlike junctions are manufactured in an arrayed fashion for coupling into large diameter core optical fibers for CMOS optical communications up to a few hundred meters. The manufacturing methodology and associated challenges are discussed for the scaling down of device dimensions, and difficulties in realizing the structures are investigated. The optical power characteristics are discussed as well as the spectral nature of emission along with the advantages and disadvantages thereof. This work compares different architectures of light sources that were implemented where a comparison is drawn between previous SOI devices as well as bulk CMOS. We believe the improved SOI light sources are fully compatible with modern CMOS technologies based on SOI and may provide such technologies with a much needed light source as part of the circuit designer’s toolkit.

In this paper we review our recent progress in two complementary approaches to photodetectors on silicon photonic chips for on-chip optical interconnection applications, namely epitaxially grown III-V-on-silicon and all-silicon microcavity-enhanced photodetectors, both for the 1550nm wavelengths. On the epitaxially grown III-V-on-silicon photodetectors front, we have demonstrated both normal-incidence and waveguide-butt-coupled p-i-n photodetectors. We simulate the silicon waveguide butt-coupling to the InGaAs absorption region and estimate the absorption efficiency using a three-dimensional finite-difference time-domain method. We optimize the InGaAs absorption region in order to attain a bandwidth of 46 GHz. We also report our latest experimental demonstration of all-silicon microresonator enhanced linear-absorption photodetectors using defect-state absorption in pn-diode-integrated microresonators. Our initial experiments reveal the measured bandwidths to be exceeding 10 GHz.

This work investigates the implementation of all-optical logic gates based on optical injection locking (OIL). All-optical inverting, NOR, and NAND gates are experimentally demonstrated using two distributed feedback (DFB) lasers, a multi-mode Fabry–Perot laser diode, and an optical band-pass filter. The DFB lasers are externally modulated to represent logic inputs into the cavity of the multi-mode Fabry–Perot slave laser. The input DFB (master) lasers’ wavelengths are aligned with the longitudinal modes of the Fabry–Perot slave laser and their optical power is used to modulate the injection conditions in the Fabry–Perot slave laser. The optical band-pass filter is used to select a Fabry– Perot mode that is either suppressed or transmitted given the logic state of the injecting master laser signals. When the input signal(s) is (are) in the on state, injection locking, and thus the suppression of the non-injected Fabry–Perot modes, is induced, yielding a dynamic system that can be used to implement photonic logic functions. Additionally, all-optical photonic processing is achieved using the cavity-mode shift produced in the injected slave laser under external optical injection. The inverting logic case can also be used as a wavelength converter — a key component in advanced wavelength-division multiplexing networks. As a result of this experimental investigation, a more comprehensive understanding of the locking parameters involved in injecting multiple lasers into a multi-mode cavity and the logic transition time is achieved. The performance of optical logic computations and wavelength conversion has the potential for ultrafast operation, limited primarily by the photon decay rate in the slave laser.

GeSn LED’s with Sn contents up to 4% exhibit light emission from the direct band transition although GeSn of low Sn contents is an indirect semiconductor.. The emission wavelength is red shifted compared to Ge. The redshift of the direct band transition is confirmed by different optical characterization techniques as photoluminescence, electroluminescence, photodetection and reflectivity. The photon emission energy decreases from 0.81 eV to 0.65 eV for compressively strained GeSn of 0% to 4% Sn content. Growth of GeSn up to 12% Sn is performed for which preliminary characterization results are given.

This paper presents a novel technique for the integration of Complementary Metal-Oxide Semiconductor (CMOS) chip with a Photonic Integrated Circuit (PIC). This proposed technique is demonstrated by integrating a PIC comprising of 2X2 optical switches and a CMOS header processor, implemented in the IBM 130nm CMOS technology. The processor configures the switch fabric on the PIC allowing for the design of ultra-fast low-power optical packet switching. An innovative CMOS chip based imprinted hard mask technique, utilizing a heat curable Polydimethylsiloxane (PDMS), allows for accurate microfabrication of wafer-scale sockets. The fabricated sockets in the PIC are at-most 9 μm larger than the chip on all sides. Accurate alignment between chips is achieved by using bottom side contact lithography printer to pattern alignment marks on the backside of the chip, making the process insensitive to chip size variations. Independent temperature control of the arm and the stage in the flip-chip bonder enables localized polymerization of PDMS to form imprinted hard mask for integration of PIC with more than one CMOS chip, enabling seamless multichip integration. The horizontal gap and the vertical displacement between the chip and the PIC were 7 and 0.5 um respectively. Electrical connections between the CMOS chip and the PIC were patterned and tested both electrically and optically. These measurements show that the functionality of the PIC and the CMOS chip were not affected by the integration process.

We review our recent progress on the heterogeneous integration of high-speed InP photodiodes (PDs) on a silica-based planar lightwave circuit (PLC) with the goal of realizing a small photonic integrated circuit (PIC) device with excellent performance. Heterogeneous integration technology is a combination of monolithic InP fabrication and angled micro-mirror etching processes, and provides low-loss optical coupling between them without any complicated optical alignment. Also, by employing 2.5%-Δ waveguides with a bending radius of 1 mm, we can reduce the chip size required for compact PIC devices. We demonstrated a dual-polarization quadrature-phase-shift-keying (DP-QPSK) coherent detector composed of a variable optical attenuator (VOA), a polarization beam splitter (PBS), eight high-speed PDs, two 90-degree optical hybrids (OHs) and micro-mirrors. Heterogeneous technology on silica-based PLCs will be an attractive way to provide compact high performance PICs for future photonic networks.

Silicon nanophotonic platform based on a silicon-on-insulator substrate enables dense photonic integration due to transparency for light propagation and ultra-high refractive index contrast for light confinement. Here, we integrate silicon together with III-V for high-efficiency heterogeneous Silicon/III-V and short vertical optical interconnect access. The fabrication involves 3 critical processes: 1) obtaining more than 80% maximum bonded areas of Si with III-V, 2) precise alignment of III-V nano-devices on top of the passive devices and 3) vertical sidewall etch profile of Si and III-V devices. The measurement results show around 90% coupling efficiency. The realization of this heterogeneous Si/III-V integration platform will open up enormous opportunities for photonic system on silicon through integrating various devices.

Performance scalability of computing systems built upon chip multiprocessors are becoming increasingly constrained by limitations in power dissipation, chip packaging, and the data throughput achievable by the interconnection networks. In particular, today’s systems based on electronic interconnects suffer from a growing memory access bottleneck as the speed at which processor-memory data can be communicated out of the chip package is severely bounded. Silicon photonics provide a CMOS-compatible solution for integrating high bandwidth-density off-chip optical I/O which can overcome some of these packaging limitations while adhering to pJ/bit-scale power efficiency requirements. Microrings in particular pose an attractive option for realizing optical communication functionalities due to their low footprint, low power dissipation, and inherent WDM-suitability due to their wavelength-localized operation. We analyze a terabit-per-second scale microring-based optical WDM link composed of current best-of-class devices. Our analysis provides quantitative measures for the maximal achievable bandwidth per link that could be reasonably realized within several years. We account for the full optical power budget to determine the achievable bandwidth as well as to enable a power consumption analysis including transmit and receive circuitry, photonic-device power dissipation, and laser power. The results highlight key device attributes that require significant advancement and point out the need for improvements in laser wall-plug efficiencies to provide sub-pJ/bit scale optical links.

Optical channelizing filters with narrow linewidth are of interest for optical processing of microwave signals. Fabrication tolerances make it difficult to place exactly the optical resonance frequency within the microwave spectrum as is required for many applications. Therefore, efficient tuning of the filter resonance is essential. In this paper we present a tunable ring resonator filter with an integrated semiconductor optical amplifier (SOA) fabricated on an InP based photonic integrated circuit (PIC) platform. The ring resonance is tuned over 37 GHz with just 0.2 mA of current injection into a passive phase section. The use of current injection is often more efficient than thermal tuning using heaters making them useful for low-power applications. The single active ring resonator has an electrical FWHM of 1.5 GHz and shows greater than 16 dB of extinction between on and off resonance. The effects of SOA internal ring gain and induced passive loss on extinction and linewidth will be shown. Agreement between experimentally demonstrated devices and simulations are shown. The integration of the active and passive regions is done using quantum well intermixing and the resonators utilize buried heterostructure waveguides. The fabrication process of these filters is compatible with the monolithic integration of DBR lasers and high speed modulators enabling single chip highly functional PICs for the channelizing of RF signals.

An effective simulation and design platform is presented in this paper for semiconductor plasmonic nanodisk laser. The three-dimensional laser structure is modeled and simulated with a body-of-revolution finite-difference-timedomain (BOR-FDTD) combined with the multi-level gain medium model and the Drude-Lorentz metal model, which gives a comprehensive spatial and temporal electromagnetic simulation of the nano-cavity and its lasing performance above the threshold. A semiconductor plasmonic nano-disk laser embedded in silver film is designed and the spatial and temporal lasing performance is numerically demonstrated. The physical volume of the nanodisk laser is only 1.17 (λ/2n)³ (a diameter of 200 nm and a height of 300 nm) and it has lasing wavelength at 1400 nm with a pumping threshold of 0.4 μW.