This PDF file contains the front matter associated with SPIE Proceedings Volume 8166, including the Title Page, Copyright information, Table of Contents, and the Conference Committee listing.

A survey supported by SEMATECH and administered by David Powell Consulting was sent to microelectronics industry leaders to gather information about the mask industry as an objective assessment of its overall condition. The survey was designed with the input of semiconductor company mask technologists and merchant mask suppliers. This year's assessment is the tenth in the current series of annual reports. With ongoing industry support, the report has been used as one of the baselines to gain perspective on the technical and business status of the mask and microelectronics industries. It continues to serve as a valuable reference to identify the strengths and opportunities of the mask industry. The results will be used to guide future investments pertaining to critical path issues. This year's survey was essentially the same as the 2005 through 2010 surveys. Questions are grouped into following categories: General Business Profile Information, Data Processing, Yields and Yield Loss Mechanisms, Delivery Times, Returns, and Services. Within each category are multiple questions that result in a detailed profile of both the business and technical status of the critical mask industry. This profile combined with the responses to past surveys represents a comprehensive view of changes in the industry.

First experimental evidence is given that a second generation blank inspection tool has missed a number of printing reticle defects caused by an imperfection of its EUV mirror, i.e., so-called multi-layer defects (ML-defects). This work continued to use a combination of blank inspection (BI), patterned mask inspection (PMI) and wafer inspection (WI) to find as many as possible printing defects on EUV reticles. The application of more advanced wafer inspection, combined with a separate repeater analysis for each of the multiple focus conditions used for exposure on the ASML Alpha Demo Tool (ADT) at IMEC, has allowed to increase the detection capability for printing ML-defects. It exploits the previous finding that ML-defects may have a through-focus printing behavior. They cause a different grade of CD impact on the pattern in their neighborhood, depending on the focus condition. Subsequent reticle review is done on the corresponding locations with both SEM (Secondary Electron Microscope) and AFM (Atomic Force Microscope). This review methodology has allowed achieving clear evidence of printing ML defects missed by this BI tool, despite of a too high nuisance rate, reported before. This establishes a next step in the investigation how essential actinic blank inspection (ABI) is. Presently it is the only known technique whose detection capability is considered independent from the presence of a (residual) distortion of the multi-layer at the top surface. This is considered an important asset for blank inspection, because the printability of a ML-defect in EUV lithography is determined by the distortion throughout the multilayer, not that at the top surface.

Despite significant progress in the commercialization of extreme ultraviolet (EUV) lithography, many important challenges remain, including in the area of masks. The issue of EUV phase roughness that can arise from either multilayer or capping layer roughness has recently garnered increasing concern. The problem with mask phase roughness is that it couples line-edge roughness (LER) through the formation of image plane speckle. The coupling from phase roughness to LER depends on many factors including roughness magnitude, roughness correlation length, illumination partial coherence, aberrations, defocus, and numerical aperture. Analysis shows that only on the order of 50 pm multilayer roughness may be tolerable at the 22-nm half-pitch node. Results also show that Atomic Force Microscopy (AFM) may not be a suitable method for measuring mask phase roughness due to its sensitivity to the surface only. Capping layer roughness is another significant concern especially given that it has been shown to increase with cleaning cycles. In this case, however, AFM does provide a reasonable metric.

We had developed an actinic full-field inspection system to detect multilayer phase-defects with dark field imaging. Regarding the actinic inspection of native defects, the influence of the defect's surface dimension and multilayer structure, on the intensity-signal obtained from the inspection was analyzed. Three mask blanks were inspected from which 55 defects, observed with AFM and SEM, were classified as amplitude-defects or phase-defects. The surface dimensions and SEVDs (sphere equivalent volume diameters) of the defects were measured with the AFM. In the case where their SEVDs were same as of the programmed phase-defects, they were found to produce stronger intensitysignals in comparison to the ones from the programmed phase-defects. Cross-sectional multilayer structures of two native phase-defects were observed with TEM, and those defects formed non-conformal structures in the multilayer. This result means that most of the native phase-defects tend to form a non-conformal structure, and can make large impact on the wafer image in comparison to the ones from a conformal structure. Besides phase-defects, the actinic inspection also detected amplitude-defects. Although the sensitivities of the amplitude-defects were found to be lower than those of the phase-defects, an amplitude-defect higher than 30 nm could be detected with high probability.

We describe the characterization of native phase defects in the manufacturing of extreme ultraviolet (EUV) mask blanks using the state-of-the-art mask metrology equipment in SEMATECH's Mask Blank Development Center (MBDC). We used commercially available quartz substrates and deposited Mo/Si multilayers on the substrates to characterize phase defects. We also prepared programmed defects of various dimensions using e-beam patterning technology on which multilayers were deposited. Transmission electron microscopy (TEM) was used to study multilayer profile changes, while SEMATECH's actinic inspection tool (AIT) was used to image defects and predict their printability. Defect images at different focal depths of the AIT are correlated to TEM cross sections and atomic force microscopy (AFM) dimensions. The printability of native and programmed defects was also investigated.

Many efforts in EUV are currently focused on detecting and reducing defects on blanks and patterned masks. Bumps and pits found on blank substrates are particularly of concern since these effectively cause phase change and often print severely under EUV conditions. With the current inspection of EUV blanks and patterned masks being primarily highresolution DUV or e-beam based, it becomes very challenging to assess the impact of the detected defects. Even with the realization of EUV AIMS^TM, expected in 2014, the nature of the buried multi-layer defect in terms of its location, size, shape, and profile will always be uncertain. In this paper, we have demonstrated several techniques that can be used for EUV defect disposition both in short- and long-term. These techniques include use of SEM images for absorber-defect disposition, and AFM images for determining the printability of buried defects. In the case of absorber defects, the SEM image of the defect is processed through a novel contour-extraction algorithm which accurately extracts the contours of the defective and generates the contour of the reference patterns. The mask contours are then simulated in Luminescent's EUV Defect Printability Simulator (DPS), a fast and accurate EUV simulator, and the EUV aerial images subsequently analyzed in the Aerial Image Analyzer (AIA). For buried defects, models characterizing the growth of the multi-layer defect from substrate and multi-layer to the surface have been developed and can be calibrated in several ways, including using cross-sectional TEM profiles of buried defects. Using the calibrated buried defect growth model then, and the surface profile of the buried defect as indicated in the SEM and AFM images, the exact nature of the buried defect is "recovered". Knowing the profile of the buried pit or bump defect through the multi-layer then allows estimation of its printability impact in DPS. Furthermore, this also enables computing changes that could be then made to the absorber pattern in order to compensate for the buried defect printability, i.e., in Luminescent's Multi-layer Defect Compensation (MDC). This technique of inverting to the shape and height of the buried defect can also be refined later once EUV aerial images are available. While defectivity on EUV masks is currently the #1 concern in its high-volume adoption, disposition of the detected defects to EUV conditions is also very crucial. The proposed disposition techniques using Computation Lithography can be used in combination with print-tests to make the overall EUV mask defect handling flow manufacturable.

One of key deliverables of foundry based manufacturing is low cycletime. Building new and enhancing existing products by mask changes involves significant logistical effort, which could be reduced by standardizing data management and communication procedures among design house, mask shop, and foundry (fab) [1]. As an example, a typical process of taping out can take up to two weeks in addition to technical effort, for database handling, mask form completion, management approval, PO signoff and JDV review, translating into loss of revenue. In order to reduce this delay, we are proposing to develop a unified online system which should assist with the following functions: database edits, final verifications, document approvals, mask order entries, and JDV review with engineering signoff as required. This would help a growing number of semiconductor products to be flexibly manufactured at different manufacturing sites. We discuss how the data architecture based on a non-relational database management system (NRDMBS) extracted into a relational one (RDMBS) should provide quality information [2], to reduce cycle time significantly beyond 70% for an example 2 week tapeout schedule.

Critical dimensions (CD) measured in resist are key to understanding the CD distribution on photomasks. Vital to this understanding is the separation of spatially random and systematic contributions to the CD distribution. Random contributions will not appear in post etch CD measurements (final) whereas systematic contributions will strongly impact final CDs. Resist CD signatures and their variations drive final CD distributions, thus an understanding of the mechanisms influencing the resist CD signature and its variation play a pivotal role in CD distribution improvements. Current technological demands require strict control of reticle critical dimension uniformity (CDU) and the Advanced Mask Technology Center (AMTC) has found significant reductions in reticle CDU are enabled through the statistical analysis of large data sets. To this end, we employ Principle Component Analysis (PCA) - a methodology well established at the AMTC¹- to show how different portions of the lithographic process contribute to CD variations. These portions include photomask blank preparation as well as a correction parameter in the front end process. CD variations were markedly changed by modulating these two lithographic portions, leading to improved final CDU on test reticles in two different chemically amplified resist (CAR) processes.

A wafer's printed CD error can be impacted by unaccounted mask making process variation. Unaccounted mask CD and/or corner rounding alters the intended drawn mask pattern contributing to a wafer's printed CD error. During OPC wafer calibration, average mask bias and corner rounding are accounted for in the OPC model, but random local mask making process variations or mask-to-mask variations can be difficult to account in such model calibration. Thus when a wafer's CD has error, it can be difficult to determine if the general root cause was due to mask or wafer or both. An in-line monitoring application has been developed to extract accurate mask CD and rendered mask polygon from collected mask CD-SEM images. Technical information will be presented on the challenges of accurately extracting information from SEM images. In particular, discussions include SEM image calibration, contour extraction, inverse pattern rendering, and general image processing to account for mask SEM aberrations (translation, rotation, & dilation), tool-to-tool variation, vendor-to-vendor variation, run-to-run variation, and dark/bright field pattern-to-pattern variation. After accurate mask SEM contours are obtained, lithographic simulations are performed on extracted polygon contours to determine the impact of mask variation on wafer CD. This paper will present detail information about the Inverse Pattern Rendering (IPR) capabilities developed for a virtual Wafer CD (WCD) application and its results, which is proven to achieved 0.5 nm accuracy across multiple critical layers from 28 nm to 40 nm nodes on multiple CD-SEM tools over multiple mask shop locations.

Lithographic patterning encounters growing challenges to meet the requirements of current and future semiconductor technology nodes. Even e-beam lithography is challenged due to the physical characteristic of the whole transfer process including the e-beam blur, electron scattering, and resist effects. These effects cause an unavoidable blurring of the exposed shapes and are often described as process proximity effect. Besides the correction of this process proximity effect pattern contrast and process window for the lithography step have to be regarded. There are promising approaches for contrast enhancing proximity effect correction concepts. To enable a stable patterning great efforts have to be put into decreasing the errors of all involved technologies. The blurring resulting from the transfer process is usually described by a so-called process proximity function (PPF) and mostly approximated by a superposition of two or more Gaussian functions. All algorithms for proximity effect correction use that PPF to perform their correction. Thus, an accurate determination of that PPF contributes to reducing the error budget of the proximity effect correction scheme. Several methods for PPF calibration were introduced in the past. Some are based on modelling the transfer process and performing Monte Carlo simulations. Another common approach is to design and expose calibration patterns, measure the resulting CDs, and obtain the process proximity function as the result of a simulation based parameter fitting to a model function such as a sum of Gaussian functions. In order to respect the increased accuracy requirements an even more accurate description of the PPF is expected. This paper describes the newly developed PPF-explorer method for the calibration of a pointwise proximity function as a complementary technique, which is based on the exposure and evaluation of new calibration layouts. Following the common assumption that a process proximity function is radial-symmetric, we developed radial-symmetric calibration layouts.

The introduction of EUV lithography into the semiconductor fabrication process will enable a continuation of Moore's law below the 22nm technology node. EUV lithography will, however, introduce new sources of patterning distortions which must be accurately modeled and corrected with software. Flare caused by scattered light in the projection optics result in pattern density-dependent imaging errors. The combination of non-telecentric reflective optics with reflective reticles results in mask shadowing effects. Reticle absorber materials are likely to have non-zero reflectivity due to a need to balance absorber stack height with minimization of mask shadowing effects. Depending upon placement of adjacent fields on the wafer, reflectivity along their border can result in inter-field imaging effects near the edge of neighboring exposure fields. Finally, there exists the ever-present optical proximity effects caused by diffractionlimited imaging and resist and etch process effects. To enable EUV lithography in production, it is expected that OPC will be called-upon to compensate for most of these effects. With the anticipated small imaging error budgets at sub-22nm nodes it is highly likely that only full model-based OPC solutions will have the required accuracy. The authors will explore the current capabilities of model-based OPC software to model and correct for each of the EUV imaging effects. Modeling, simulation, and correction methodologies will be defined, and experimental results of a full model-based OPC flow for EUV lithography will be presented.

Mask manufacturers are continuously challenged as a result of the explosive growth in mask pattern data volume. This paper presents a new pipelined approach to mask data preparation for inspection that significantly reduces the data preparation times compared to the conventional flows used today. The focus of this approach minimizes I/O bottlenecks and allows for higher throughput on computer clusters. This solution is optimized for the industry standard OASIS.MASK format. These enhancements in the data processing flow, along with optimizations in the data preparation system architecture, offer a more efficient and highly scalable solution for mask inspection data preparation.

Mask shops perform the QoR analysis of the fractured data by measuring the quality of the various basic metrics like the shot count, sliver count, smashed figure count, file size, shot perimeter, sliver perimeter, number of thin slivers etc. Other than the basic metrics mentioned above, the QoR of fractured data is also judged upon more advanced quality metrics like the number of CD splits, number of embedded and shoreline slivers as well as the lengths of embedded and shoreline slivers. Computation of these advanced metrics involves complex and compute-intensive algorithms, especially because the fractured mask data sizes have already reached hundreds of GBs. Hence, an efficient distributed processing solution with fast turn-around-time is required to measure the overall QoR metrics of fractured data solutions. This paper clearly describes the definitions of various QoR metrics and then describes parallelizable schemes to measure these QoR metrics. Another important QoR metric of the fractured data is the orientation-independent fracturing uniformity. Fracturing uniformity plays a significant role in ensuring CD uniformity. This paper introduces the concept of fracturing uniformity and discusses the issues in detecting the same.

The increasing complexity of RET solutions with each new process node has increased the shot count of advanced photomasks. In particular, the introduction of inverse lithography masks represents a significant increase in mask complexity. Although shot count reduction can be achieved through careful management of the upstream OPC strategy and improvement of fracture algorithms, it is also important to consider more dramatic departures from traditional fracture techniques. Optimization based fracture allows for overlapping shots to be placed in a manner that allows the mask intent to be realized while achieving significant savings in shot count relative to traditional fracture based methods. We investigate the application of Optimization based fracture to reduce the shot count of inverse lithography masks, provide an assessment of the potential shot count savings, and assess its impact on lithography process window performance.

Traditionally, Variable Shape Electron Beam (VSEB) mask writing tools generate pixel-based optical proximity correction (OPC) or inverse lithography technology (ILT) masks by first simplifying them into a rectilinear polygon, and then partitioning the rectilinear polygon into shots. However, as these masks are complex and curvilinear, this approach results in an explosion of shot count and mask write time, and a loss of optimality of the OPC solution. In this work we propose an alternative fracturing approach to minimize mask write time in which the shot location, size, and dose are determined using the mask fabrication model. In doing so we allow shots to overlap in order to reduce the shot count while maintaining mask and wafer quality. Our approach is based on overcomplete signal expansion algorithms which have traditionally been used for sparse representation and compression of images and videos. Our simulation results on a 45nm random logic and contact hole circuit show shot count reduction by as much as 50%.

An illuminator and mask patterns were optimized (SMO) to minimize CD variation of a set of contact patterns selected from logic layouts and an array of SRAM cells. MEEF and defocus characteristics of the target patterns were modeled as functions of constraints on minimum mask features and spaces (MRC). This process was then repeated after linearly shrinking the input patterns by 10%. Common statistical measures of CD control worsen as MRC becomes more restrictive, but these are weak indicators compared to behavior at points in the image that exhibit high MEEF or low depth of focus. SMO solutions for minimum MEEF and maximum depth of focus are different, so some compromise is necessary. By including exposure time among the variables to be optimized, some control over local mask bias is made available to minimize MEEF and loss of litho quality due to MRC.

Complex illuminators used for optical lithography or lithographic simulators typically have a slight loss of fidelity when compared to the original illuminator design. It is usually not obvious what the lithographic effects of this loss of fidelity will be. A series of computer-designed illuminators with multiple intensity levels was designed and built for use in an Aerial Image Measurement System^1,2 (AIMS^TM)⁺. Images of the various illuminators were recorded and correlated with the original designs. Images of photomasks with programmed defects were captured using these illuminators and the results were compared with simulations using the physical illumination pattern and the ideal illumination design. The results showed that small deviations between the illuminator design and the physically constructed illuminator had very little effect on the aerial images or defect sensitivity. Larger deviations from the illuminator design have increasingly significant effects on defect sensitivity.

Litho-etch-litho-etch (LELE) is the double patterning (DP) technology of choice for 20 nm contact, via, and lower metal layers. We discuss the unique design and process characteristics of LELE DP, the challenges they present, and various solutions. ○ We examine DP design methodologies, current DP conflict feedback mechanisms, and how they can help designers identify and resolve conflicts. ○ In place and route (P&R), the placement engine must now be aware of the assumptions made during IP cell design, and use placement directives provide by the library designer. We examine the new effects DP introduces in detail routing, discuss how multiple choices of LELE and the cut allowances can lead to different solutions, and describe new capabilities required by detail routers and P&R engines. ○ We discuss why LELE DP cuts and overlaps are critical to optical process correction (OPC), and how a hybrid mechanism of rule and model-based overlap generation can provide a fast and effective solution. ○ With two litho-etch steps, mask misalignment and image rounding are now verification considerations. We present enhancements to the OPCVerify engine that check for pinching and bridging in the presence of DP overlay errors and acute angles.

At the early stage of development of semiconductor memory devices, design rule should be defined for providing design guidelines to the design engineers. Those design rules are usually expressed in terms of minimum sizes of simple patterns which describe lithography and process limitations. However the real chip designs consist of a variety of complex patterns, so minimum size design rules of simple patterns are not enough for optimizing design layout. Therefore, design rules considering various design patterns are more advisable rather than simple minimum rules. But it is not easy to setup those design rules due to the difficulties of a large number of pattern verification. In our work, we evaluate design rule verification procedure by using Design Based Metrology (DBM) to overcome the difficulties of inspecting many type of patterns. We designed a large number of test patterns including various 1D and 2D design structure. And those patterns could be inspected at a fast speed with a design based metrology. From all the measurement data, the proper design rules successfully introduced and verified. Finally we found out the suggested procedure is a suitable method for verifying design rules.

In this paper we will present ASML's holistic approach to lithography for EUV. This total approach combines the various components needed to achieve the correct on-product demands of our customers in terms of patterning fidelity across the entire image field and across the entire wafer. We will start giving a general update on ASML's NXE scanner platform of which the 6^th NXE:3100 systems is now being shipped to a leading chipmaker. The emphasis will be on wafer imaging results for various applications such as flash memory and logic's SRAM. Then we will describe the second holistic component, NXE-computational lithography, which was developed to speed-up early learning on EUV and to achieve high accuracy on the wafers. Thirdly, the YieldStar angular-resolved scatterometry tool that supports the scanner's stability was used to characterize the system and calibrate the models. The wafer-results reveal in detail predicted imaging effects of NXE lithography and allow a calibration of system parameters and characterization of hardware components. We will demonstrate mask-induced imaging effects and propose an improvement of the current EUV blank or mask-making processes.

The high volume device manufacturing infrastructure for the 22nm node and below based on EUVL technology requires defect-free EUV mask manufacturing as one of its foundations. The EUV Mask Infrastructure program (EMI) initiated by SEMATECH has identified an actinic measurement system for the printability analysis of EUV mask defects to ensure defect free mask manufacturing and cost-effective high-volume EUV production as an infrastructural prerequisite for the EUVL roadmap ([1], [2]). The Concept and Feasibility study for the AIMS^TM EUV resulted in a feasible tool concept for 16nm defect printability review. The main development program for the AIMS^TM EUV has been started at Carl Zeiss leading to a commercialized tool available in 2014. In this paper we will present the status of the progress of the design phase of this development and an infrastructure progress update of the EUV Mask defect printability review.

Due to the absence of defect-free blanks in extreme ultraviolet (EUV) lithography, defect mitigation is necessary before mass production. Currently almost all the defect mitigation methods are focused on mitigating the defect impact of one blank on one design. However, since the EUV mask vendors always have multiple designs and blanks in hand, it is also very important to consider all designs and blanks together to mitigate the total defect impact. This paper proposes a new EUV mask preparation strategy which optimally matches a set of defective blanks with multiple designs to mitigate the total defect impact. In the first step, an efficient layout relocation algorithm is adopted to minimize the defect impact of each blank on each design. Then, depending on whether blank defects are allowed to be compensated, we formulate the two different types of design-blank matching problems as flow problems and solve them optimally. Compared to sequential matching, the proposed simultaneous matching strategy shows advantages in both blank utilization and defect compensation cost minimization.

Extreme ultraviolet (EUV) e-beam patterned mask inspection (EBPMI) has been proposed by Applied Materials as a cost-effective solution for high volume manufacturing (HVM) in mask shops and fabs. Electron beam inspection technology is currently available for wafers. A recent publication described a successful sensitivity study of EUVs mask using a technology demonstration platform. Here we present a new study using extreme e-beam conditions to show the feasibility of using EBPMI in HVM. We examine potential changes in the reflectivity at the EUV wavelength after exposure to high e-beam currents, demonstrating that reflectivity does not change due to e-beam scanning. We therefore conclude that under the conditions tested, which include typical as well as extreme conditions, there is no evidence of mask damage.

Main Topics of a photomask have been CD(Critical Dimension), Overlay and Defects. In side of defects, technique suppressing growing defects which are occurring on a mask surface becomes as important as defect control method during mask manufacturing process. Conventional growing defects arise out of combination of sulfuric ion on a mask surface and environmental facts such as pellicle ingredient, humidity and etc. So Mask cleaning process was driven to reduce sulfuric acid on a mask surface which source of growing defects. And actually various cleaning process has been developed through the elimination of sulfuric acid such as DI, O3 cleaning. Normally Conventional growing defects are removed using DI, SC1 or SPM cleaning according to incidence. But recently irregular growing defects are occurred which are completely distinct from conventional growing defects. Interestingly, irregular growing defects are distributed differently from conventional on a mask. They spread in isolated space patterns and reduce the transmittance so that space pattern size continuously decreased. It causes Wafer Yield loss. Furthermore, irregular growing defects are not fully removed by cleaning which is traditional removal process. In this study, we provide difference between conventional and irregular growing defects based on its characteristic and distributed formation. In addition, we present and discuss removal and control technique about irregular growing defects. For elemental analysis and study, diverse analysis tool was applied such as TEM for checking Cross-Section, AFM for checking the roughness of surface, EDAX, AES, IC for analyzing remained ions and particles on the mask and AIMS.

Megasonic energy transfer to the photomask surface is indirectly controlled by process parameters that provide an effective handle to physical force distribution on the photomask surface. A better understanding of the influence of these parameters on the physical force distribution and their effect on pattern damage of fragile mask features can help optimize megasonic energy transfer as well as assist in extending this cleaning technology beyond the 22nm node. In this paper we have specifically studied the effect of higher megasonic frequencies (3 & 4MHz) and media gasification on pattern damage; the effect of cleaning chemistry, media volume flow rate, process time, and nozzle distance to the mask surface during the dispense is also discussed. Megasonic energy characterization is performed by measuring the acoustic energy as well as cavitation created by megasonic energy through sonoluminescence measurements.

Cryogenic CO₂ aerosol cleaning being a dry, chemically-inert and residue-free process is used in the production of optical lithography masks. It is an attractive cleaning option for the mask industry to achieve the requirement for removal of all printable soft defects and repair debris down to the 50nm printability specification. In the technique, CO₂ clusters are formed by sudden expansion of liquid from high to almost atmospheric pressure through an optimally designed nozzle orifice. They are then directed on to the soft defects or debris for momentum transfer and subsequent damage free removal from the mask substrate. Unlike aggressive acid based wet cleaning, there is no degradation of the mask after processing with CO₂, i.e., no critical dimension (CD) change, no transmission/phase losses, or chemical residue that leads to haze formation. Therefore no restriction on number of cleaning cycles is required to be imposed, unlike other cleaning methods. CO₂ aerosol cleaning has been implemented for several years as full mask final clean in production environments at several state of the art mask shops. Over the last two years our group reported successful removal of all soft defects without damage to the fragile SRAF features, zero adders (from the cleaning and handling mechanisms) down to a 50nm printability specification. In addition, CO₂ aerosol cleaning is being utilized to remove debris from Post-RAVE repair of hard defects in order to achieve the goal of no printable defects. It is expected that CO₂ aerosol cleaning can be extended to extreme ultraviolet (EUV) masks. In this paper, we report advances being made in nozzle design qualification for optimum snow properties (size, velocity and flux) using Phase Doppler Anemometry (PDA) technique. In addition the two new areas of focus for CO₂ aerosol cleaning i.e. pellicle glue residue removal on optical masks, and ruthenium (Ru) film on EUV masks are presented. Usually, the residue left over after the pellicle has been removed from returned masks (after long term usage/exposure in the wafer fab), requires a very aggressive SPM wet clean, that drastically reduces the available budget for mask properties (CD, phase/transmission). We show that CO₂aerosol cleaning can be utilized to remove the bulk of the glue residue effectively, while preserving the mask properties. This application required a differently designed nozzle to impart the required removal force for the sticky glue residue. A new nozzle was developed and qualified that resulted in PRE in the range of 92-98%. Results also include data on a patterned mask that was exposed in a lithography stepper in a wafer production environment. On EUV mask, our group has experimentally demonstrated that 50 CO₂ cleaning cycles of Ru film on the EUV Front-side resulted in no appreciable reflectivity change, implying that no degradation of the Ru film occurs.

As photomask minimum feature size requirements continue to shrink, resist resolution limitations and their tradeoffs with exposure dose are critical factors. Recently, nearly every node needs a new electron beam resist, customized for exposure dose requirements while simultaneously meeting resolution specifications. Intel Mask Operations has an active program focused on screening new electron beam resists and processes. We discuss the performance metrics we use to evaluate materials and discuss the relative capabilities of the latest resists. We present fundamental resist metrics (resolution, LER and dose) as well as manufacturing process sensitivities.

The lithography challenges posed by the 20 nm and 14 nm nodes continue to place strict minimum feature size requirements on photomasks. The wide spread adoption of very aggressive Optical Proximity Correction (OPC) and computational lithography techniques that are needed to maximize the lithographic process window at 20 nm and 14 nm groundrules has increased the need for sub-resolution assist features (SRAFs) down to 50 nm on the mask. In addition, the recent industry trend of migrating to use of negative tone develop and other tone inversion techniques on wafer in order to use bright field masks with better lithography process window is requiring mask makers to reduce the minimum feature size of opaque features on the reticle such as opaque SRAFs. Due to e-beam write time and pattern fidelity requirements, the increased use of bright field masks means that mask makers must focus on improving the resolution of their negative tone chemically amplified resist (NCAR) process. In this paper we will describe the development and characterization of a high resolution bright field mask process that is suitable for meeting 20 nm and early 14 nm optical lithography requirements. Work to develop and optimize use of an improved chrome hard mask material on the thin OMOG binary mask blank¹ in order to resolve smaller feature sizes on the mask will be described. The improved dry etching characteristics of the new chrome hard mask material enabled the use of a very thin (down to 65 nm) NCAR resist. A comparison of the minimum feature size, linearity, and through pitch performance of different NCAR resist thicknesses will also be described. It was found that the combination of the improved mask blank and thinner NCAR could allow achievement of 50 nm opaque SRAFs on the final mask.. In addition, comparisons of the minimum feature size performance of different NCAR resist materials will be shown. A description of the optimized cleaning processes and cleaning durability of the 50 nm opaque SRAFs will be provided. Furthermore, the defect inspection results of the new high resolution mask process and substrate will be shared.

Phase-shifting effect of EUV masks with various absorber thicknesses has been studied both by simulations and experiments. In EUV lithography, masks with 180 phase shifting absorber work like embedded attenuated phase-shifting masks. At 66nm thickness of TaN/TaON absorber, 180 degree phase shifting can be achieved in theory. Based on the experiments, we observed that the true180 degree phase shifting can be achieved with absorber thickness between 66 and 76 nm. In this paper, phase shifting impact of the various thickness absorbers has been characterized. Imaging performance of masks with 51 nm, 66 nm and 76 nm thick absorber has been experimentally compared. The process window of various thickness absorber masks are rigorously studied.

Optical lithography stays at 193nm with a numerical aperture of 1.35 for several more years before moving to EUV lithography. Utilization of 193nm lithography for 32nm and beyond forces the mask maker to produce complex mask designs and tighter lithography specifications which in turn make process control more important than ever. High yield with regards to chip production requires accurate process control. Critical Dimension Uniformity (CDU) is one of the key parameters necessary to assure good performance and reliable functionality of any integrated circuit. There are different contributors which impact the total wafer CDU: mask CD uniformity, resist process, scanner and lens fingerprint, wafer topography, etc. In this study the newly developed wafer level CD metrology tool WLCD of Carl Zeiss SMS is utilized for CDU measurements in conjunction with the CDC tool from Carl Zeiss SMS which provides CD uniformity correction. The WLCD measures CD based on proven aerial imaging technology. The CDC utilizes an ultrafast femto-second laser to write intra-volume shading elements (Shade-In Elements^TM) inside the bulk material of the mask. By adjusting the density of the shading elements, the light transmission through the mask is locally changed in a manner that improves wafer CDU when the corrected mask is printed. The objective of this study is to evaluate the usage of these two tools in a closed loop process to optimize CDU of the mask before leaving the mask shop and to ensure improved intra-field CDU at wafer level. Main focus of the study is to investigate the correlation of applied attenuation by CDC and the resulting CD change, the impact of CDC process on CD linearity behavior and the correlation of WLCD data and wafer data. Logic and SRAM cells with features having designed line CD's at wafer level, ranging from 27nm to 42nm have been used for the study. The investigation provides evidence that the applied attenuation by CDC shows a linear correlation to CD change at wafer level measured with WLCD. Additionally, WLCD data shows that the CDC application does not impact the CD linearity for the tested feature range. The WLCD measurement data in turn show an excellent correlation to wafer print CD data indicating cost effective use case of closed loop WLCD/CDC application.

As semiconductor features shrink in size and pitch, the extreme control of CD uniformity, MTT and image placement is needed for mask fabrication with e-beam lithography. Among the many sources of CD and image placement error, the error resulting from e-beam mask writer becomes more important than before. CD and positioning error by e-beam mask writer is mainly related to the imperfection of e-beam deflection accuracy in optic system and the charging and contamination of column. To avoid these errors, the e-beam mask writer should be designed taking into account for these effects. However, the writing speed is considered for machine design with the highest priority, because the e-beam shot count is increased rapidly due to design shrink and aggressive OPC. The increment of shot count can make the pattern shift problem due to statistical issue resulting from e-beam deflection error and the total shot count in layout. And it affects the quality of CD and image placement too. In this report, the statistical approach on CD and image placement error caused by e-beam shot position error is presented. It is estimated for various writing conditions including the intrinsic e-beam positioning error of VSB writer. From the simulation study, the required e-beam shot position accuracy to avoid pattern shift problem in 22nm node and beyond is estimated taking into account for total shot count. And the required local CD uniformity is calculated for various e-beam writing conditions. The image placement error is also simulated for various conditions including e-beam writing field position error. Consequently, the requirements for the future e-beam mask writer and the writing conditions are discussed. And in terms of e-beam shot noise, LER caused by exposure dose and shot position error is studied for future e-beam mask writing for 22nm node and beyond.

Improvement of pattern placement accuracy is essential to solve upcoming challenges in mask making. Placement errors are driven by multiple effects with electron mediated resist surface charging being a major error source. Modeling this systematic effect thus allows the determination of the placement errors before plate processing. This opens the door to an effective charging compensation. In this paper we study the simulated benefit of two distinct charging compensation models in the context of full-scale mask production layouts. The potential pattern placement improvements are evaluated using actual placement results obtained without charging effect corrections. An in depth comparison of the two models is presented, demonstrating the differences in placement error prediction between using a static or a dynamic charging model. We find that substantial improvements can be achieved using the dynamic charging model. Productive implementation of this functionality is the natural next step.

Many lithography candidates, such as ArF immersion lithography with double-patterning/double-exposure techniques, EUV lithography and nano-imprint lithography, show promising capability for 22-nm half-pitch generation lithography. ArF immersion lithography with double-patterning/double-exposure techniques remains the leading choice as other techniques still lack the conclusive evidence as the practical solution for actual production. Each of the prospective lithography techniques at 22-nm half-pitch generation requires masks with improved accuracy and increased complexity. We have developed a new electron beam mask writer, EBM-8000, as the tool for mask production of 22-nm half-pitch generation and for mask development of 16nm half-pitch generation, which is necessary for the practical application of these promising lithography technologies. The development of EBM-8000 was focused on increasing throughput and improving beam positioning accuracy. Three new major features of the tool are: new electron gun with higher brightness to achieve current density of 400 A/cm², high speed DAC amplifier to accurately position the beam with shorter settling time, and additional temperature control to reduce the beam drift. The improved image placement accuracy and repeatability, and higher throughput of EBM-8000 have been confirmed by actual writing tests with our in-house tool.

According to the ITRS roadmap, semiconductor industry drives the 193nm lithography to its limits, using techniques like double exposure, double patterning, mask-source optimization and inverse lithography. For photomask metrology this translates to full in-die measurement capability for registration and critical dimension together with challenging specifications for repeatability and accuracy. Especially, overlay becomes more and more critical and must be ensured on every die. For this, Carl Zeiss SMS has developed the next generation photomask registration and overlay metrology tool PROVE® which serves the 32nm node and below and which is already well established in the market. PROVE® features highly stable hardware components for the stage and environmental control. To ensure in-die measurement capability, sophisticated image analysis methods based on 2D correlations have been developed. In this paper we demonstrate the in-die capability of PROVE® and present corresponding measurement results for shortterm and long-term measurements as well as the attainable accuracy for feature sizes down to 85nm using different illumination modes and mask types. Standard measurement methods based on threshold criteria are compared with the new 2D correlation methods to demonstrate the performance gain of the latter. In addition, mask-to-mask overlay results of typical box-in-frame structures down to 200nm feature size are presented. It is shown, that from overlay measurements a reproducibility budget can be derived that takes into account stage, image analysis and global effects like mask loading and environmental control. The parts of the budget are quantified from measurement results to identify critical error contributions and to focus on the corresponding improvement strategies.

Using various technical tricks, 193nm lithography has been pushed for the 22nm logic node. For optical and EUV lithography, the International Technology Roadmap for Semiconductors (ITRS [1]) requests a registration error below 3.8 nm for masks for single-patterning layers. Double patterning further reduces the tolerable pattern placement error to < 2.7 nm for each mask of a pair that forms one layer on the wafer. For mask metrology on the 2x node, maintaining a precision-to-tolerance (P/T) ratio of 0.25 will be challenging. The total measurement uncertainty has to be significantly below 1.0nm. In this work, results obtained during the LMS IPRO5 beta system evaluation are presented. LMS IPRO5 beta system evaluation is part of the CDUR32 project, funded by the German Federal Ministry of Education and Research. A major improvement to previous LMS IPRO generations is the new laser illumination system, which significantly improves optical resolution and contrast (especially on EUV substrates). Therefore, optical resolution and measurement capability are evaluated using standard registration targets, in-die wafer overlay targets, and arbitrary shaped features on different substrates comprising EUV and binary MoSi masks. Position measurement uncertainty for the new center of gravity (CofG) measurement algorithm, important for in-die measurement capability, is evaluated. The results are compared with results obtained using the traditional edge detection algorithm.

Defects of the multi-layer (ML) mirror on a EUV reticle, so-called ML-defects, are a prime aspect why EUV mask defectivity is considered a challenge before EUV lithography can be used for the production of future node integrated circuits. The present paper addresses the possibility to mitigate the printability of these defects by repair. Repair of natural EUV mask defects is performed using the electron beam based Carl Zeiss MeRiT® repair technology and is evaluated by wafer printing on the ASML EUV Alpha Demo Tool (ADT) installed at IMEC. Both absorber defects and ML-defects are included. The success of absorber defect repair (both opaque and clear type) is illustrated. For compensation repair of ML-defects experimental proof of the technique is reported, with very encouraging results both for natural pits and bumps. In addition, simulation is used to investigate the limitations of such compensation repair, inspired by the residual printability found experimentally. As an example it was identified that alignment of the compensation repair shape with the ML-defect position requires sub-20nm accuracy. The integration of an Atomic Force Microscope (AFM) into the repair tool has been an important asset to cope with this.

We report inspection results of EUVL masks with 193nm wavelength tools for 30nm and 24nm half-pitch nodes. The dense line and space and contact pattern is considered to study inspection capability. The evaluation includes defect contrast variation depending on illumination conditions, defect types, and design nodes. We show many inspection images with various optic conditions. Consequently, the detection sensitivity is affected by contrast variation of defects. The detection sensitivity and wafer printability are addressed with a programmed defect mask and a production mask. With these results, we want to discuss the capability of current EUVL mask inspection tools and the future direction.

The routine use of aggressive OPC at advanced technology nodes, i.e., 40nm and beyond, has made photomask patterns quite complex. The high-resolution inspection of such masks often result in more false and nuisance defect detections than ever before. Traditionally, each defect is manually examined and classified by the inspection operator based on defined production criteria. The significant increase in total number of detected defects has made manual classification costly and non-manufacturable. Moreover, such manual classification is also susceptible to human judgment and hence error-prone. Luminescent's Automated Defect Classification (ADC) offers a complete and systematic approach to defect disposition and classification. The ADC engine retrieves the high resolution inspection images and uses a decision-tree flow based on the same criteria human operators use to classify a given defect. Some identification mechanisms adopted by ADC to characterize defects include defect color in transmitted and reflected images, as well as background pattern criticality based on pattern topology. In addition, defect severity is computed quantitatively in terms of its size, impacted CD error, transmission error, defective residue, and contact flux error. The final classification uses a matrix decision approach to reach the final disposition. In high volume manufacturing mask production, matching rates of greater than 90% have been achieved when compared to operator defect classifications, together with run-rates of 250+ defects classified per minute. Such automated, consistent and accurate classification scheme not only allows for faster throughput in defect review operations but also enables the use of higher inspection sensitivity and success rate for advanced mask productions with aggressive OPC features.

Regardless at what technology node it will be implemented, extreme ultraviolet (EUV) lithography appears to be the most likely candidate to succeed 193 nm wavelength lithography. However, EUV photomasks present new and different challenges for both repair and clean processes. Among these are different and more complex materials, greater sensitivity to smaller topography differences, and lack of pelliclization to protect critical pattern areas. Solutions developed and recently refined to meet these challenges are reviewed as an integrated solution to make the manufacture and maintenance of this mask type feasible. This proven, integrated solution includes nanomachining, BitClean® and cryogenic clean processes applied for hard (missing pattern) and soft (nanoparticle) defect removals with no damage to underlying multilayers.

Historically, photomask and wafer cleaning have been considered trivial tasks. The primary challenge had been simply the removal of particles that may have an impact on final product yield. As wavelengths decrease and energy on the image plane of the reticle increase, the degree and complexity of surface contaminants on the reticle become a more complicated challenge. The result is that the mask fabricator is faced with two new challenges; reducing and identifying the types of contaminants on the reticle prior to exposure in the wafer fab and eliminating contaminants that have been deposited in the fab. These contaminants are often different in that 193nm exposure produces higher molecular weight contaminants that can be more difficult to remove. While the effects of these contaminants may not be serious for transmissive lithography, their effects can be catastrophic for reflective lithography, such as Extreme Ultra- Violet (EUV) lithography. We will provide results showing the types of contaminants commonly found on various types of reticles and the respective challenges associated with their removal. Additionally, prior to developing an effective cleaning protocol understanding the chemical composition of the substrate is extremely important. We will provide analytical data that will clearly describe the composition of the mask substrates.

In mask manufacturing process, some soft defects generated through co-interaction of dry etch and PR coating are hard to be removed in the conventional cleaning or repair process. It is on MoSi layer with smooth surface (lower roughness than MoSi), very thin and higher transmittance than MoSi film, it looks like half-tone pin-hole. Also, the defects are hard to detect in the conventional PSM inspection tool because of its thin and higher transmittance. In this paper, the root cause and control method of dry etch related half-tone pin-hole like soft defect is studied.

EUV masks include many different layers of various materials rarely used in optical masks, and each layer of material has a particular role in enhancing the performance of EUV lithography. Therefore, it is crucial to understand how the mask quality and patterning performance can change during mask fabrication, EUV exposure, maintenance cleaning, shipping, or storage. The fact that a pellicle is not used to protect the mask surface in EUV lithography suggests that EUV masks may have to undergo more cleaning cycles during their lifetime. More frequent cleaning, combined with the adoption of new materials for EUV masks, necessitates that mask manufacturers closely examine the performance change of EUV masks during cleaning process. We have investigated EUV mask quality and patterning performance during 30 cycles of Samsung's EUV mask SPM-based cleaning and 20 cycles of SEMATECH ADT exposure. We have observed that the quality and patterning performance of EUV masks does not significantly change during these processes except mask pattern CD change. To resolve this issue, we have developed an acid-free cleaning POR and substantially improved EUV mask film loss compared to the SPM-based cleaning POR.

EUV lithography (EUVL) is considered the most attractive solution for semiconductor device manufacturing beyond the 22nm half-pitch node. In EUVL, one of the greatest challenges is the lack of a pellicle, which makes EUV masks prone to particle contamination. Therefore, mask cleaning plays an important role in keeping masks clean during both fabrication in the mask shop and usage in the wafer fab. According to the International Technology Roadmap for Semiconductors (ITRS), in 2013 mask cleaning processes should remove all defects larger than 25nm without damaging 78nm and smaller patterns for the 23nm Flash half-pitch node [1]. In addition to contamination concerns, EUV masks introduce new materials and a multilayer structure that is different from the Cr on glass used in traditional optical masks. Physical forces applied by megasonic cleaning to remove particles on an optical mask could damage EUV mask patterns. Thus, it is important to determine the magnitude of the physical forces that can break absorber patterns (TaN or TaBN) from the surface of a Ru-capped MoSi multilayer film. The adhesion of particles of interest to the Ru-capped multilayer should also be measured. In the complex structure of an EUV mask, adhesion forces of particles on the top surface are modified by the different layers beneath the Ru. Hence, it is crucial to directly measure the force required to remove particles and break absorber patterns on EUV mask surfaces to determine the process window for applicable cleaning forces. We used scanning probe microscopy (SPM) to quantify these forces. The SPM probe was precisely controlled to remove particles and break patterns on Ru-capped EUV mask blanks. While being manipulated, the deflection signals of the probe were monitored and then converted to forces using a simple beam model. In this paper, we present the measured breakage forces for absorber patterns as a function of their size and compare them with removal forces for 50nm and 100nm SiO2 and polystyrenelatex (PSL) particles. Based on these data and our analysis, we will demonstrate a process window for physical force that can successfully clean EUV masks beyond the 16nm half-pitch node.

In this study, the impact of repetitive cleaning of EUV masks on reflectivity, surface roughness and lithographic performance was evaluated. Two masks were fabricated and patterned with the same layout using commercially available EUV blanks; one was subjected to 33 cleaning cycles and the other was kept as a reference. Wafers were patterned using both masks on the SEMATECH Berkeley 0.3 NA micro-field exposure tool (MET), and the data was used to determine process latitude and line edge roughness at regular intervals between cleaning cycles. Additionally, mask surface roughness and EUV reflectivity were also measured. After a total of 33 cleaning cycles, minimal degradation was observed in lithographic performance compared to the reference mask, as well as surface roughness and reflectivity.

Currently, scatterometry in semiconductor industry is performed in the visible and UV spectral ranges and is used to monitor process variations in production and development. The new challenge is to establish scatterometry as a traceable and absolute metrological method for dimensional measurements on semiconductor photomasks. In scatterometry, the properties of the photomasks structures are derived from an optimization which minimizes the difference between the measured scatter intensities and intensities calculated by numerical methods like FEM. We demonstrate that the inclusion of the roughness into the model provides simultaneously a better structure reconstruction and information on the structure roughness. The inclusion of the roughness is essential for the quality of the structure reconstruction from angular resolved scatterometry. Scattering with short wavelength radiation increases the sensitivity to structure details. Small angle X-ray scattering (SAXS) was already used in transmission mode for CD measurements at wafers. We used grazing incidence SAXS (GISAXS), i.e. the measurement of the scatter around the reflected X-ray beam in total reflection geometry for the characterization of EUV photomasks. We demonstrate the GISAXS diffraction pattern of periodic lines for large optical diffraction gratings to point out how generally structure parameters show up in these measurements. For absorber lines at an EUV test mask, the scatter figures became rather complex due to contributions from the various layers and surface structures of the mask. It is shown that GISAXS allows to derive geometrical properties and layer thicknesses for structured surface in a direct way without the need for numerical modelling. The information of SAXS can be used to complement EUV scatterometry. Particularly, it provides independent information on roughness and layer structures.

EUV scatterometry is performed on 3D patterns on EUV lithography masks. Numerical simulations of the experimental setup are performed using a rigorous Maxwell solver. Mask geometry is determined by minimizing the difference between experimental results and numerical results for varied geometrical input parameters for the simulations.

In next generation lithography (NGL) for the 22nm node and beyond, the three dimensional (3D) shape measurements of side wall angle (SWA) and height of the photomask pattern will become critical for controlling the exposure characteristics and wafer printability. Until today, cross-section SEM (X-SEM) and Atomic Force Microscope (AFM) methods are used to make 3D measurements, however, these techniques require time consuming preparation and observation. This paper presents an innovative technology for 3D measurement using a multiple detector CDSEM and reports its accuracy and precision.

Optical Proximity Correction (OPC) becomes complicated, shrinking a design rule. As a result, measurement points have increased, and improving the OPC model quality has become more difficult. To improve OPC simulation cost, Contour-based OPC-modeling is superior to CD-based, because Contour-based shape based rich information. Hence, Contour-based OPC-modeling is imperative in the next generation lithography, as reported in SPIE2010[5]. In this study, Mask SEM-contours were input into OPC model calibration in order to verify the impact of mask pattern shape on the quality of the OPC model. Advanced SEM contouring technology was applied to both of Wafer CD-SEM and Mask CD-SEM in examining the effectiveness of OPC model calibration. The evaluation results of the model quality will be reported. The advantage of Contour based OPC modeling using Wafer SEM-Contour and Mask SEM-Contour in the next generation computational lithography will be discussed.

38nm half pitch pattern was replicated from Si master pattern to quartz blank template. It is a novel approach different from typical quartz to quartz replication. This replication concept is expected to alleviate the burden not only in cost but also resolution for NIL template fabrication. In this study, full field Si master fabricated by ArF immersion lithography, UV-transparent hard mask for quartz blank template and core-out quartz blank template were applied to prove the concept. And the replica template was evaluated with NIL and subsequent etching.

We have been developing nanoimprint templates for the next-generation sub-20nm nanofabrication technology, with particular emphasis on duplicate fabrication of quartz templates created from Si masters. In general, the narrowing of pattern line widths is accompanied by concerns about whether resist will sufficiently fill such lines. Our development has concentrated on the filling property of resist in narrow lines and on pattern shape after release from the mold. Our findings indicated that pattern formability differs according to the type of resist monomer. We inferred that these differences are manifested in such behaviors as resist shrinkage after or during release of the mold. Using a novel resist that has good formability, we pursued quartz template duplication that employs UV-NIL. As a result, we demonstrated HP20nm quartz pattern formation using the duplication process. We were also verified NIL resist pattern resolution of HP17.5nm.

Mask defectivity is often highlighted as one of the barriers to a manufacturable EUV solution. As EUV lithography matures, other components of mask making also emerge as key focus areas in the industry: critical dimension (CD) control, film variability, selectivity, and profile tolerance. Mask materials and specifications continue to evolve to meet the unique challenges of EUV lithography, creating the need for etch capabilities that can keep pace with the latest developments. In this study, the performance of a new EUV mask etch system will be evaluated using a variety of mask blanks to determine the relative performance of each blank type. Etch contributions to mean to target (MTT), CDU, linearity, selectivity, capping layer uniformity, line edge roughness (LER), and profile quality will be characterized to determine tool performance. The new system will also be used to demonstrate multilayer etching capabilities, important for opaque frame and alternating phase shift applications. A comprehensive summary of the etch performance of various EUV films and the readiness for manufacturing applications will be provided.

As part of 20 nm/22 nm process development, an evaluation was performed to determined the impact of Thin OMOG on mask inspection. Despite significant improvements in mask inspectability and reduced database modeling errors, thin OMOG demonstrated lower defect sensitivity as compared to Standard OMOG at the same inspection conditions (calibration, sensitivity). Stack height aside, the primary difference between standard and thin OMOG is attenuator reflectivity. It is surmised that the reduction in sensitivity is due to a lower reflected light contrast on thin-OMOG. This characteristic was noted for both 257 nm and 193 nm inspection wavelengths. In addition to the reduction in defect sensitivity, an unexpected phase interference was noted at the image edge with a 193 nm inspection wavelength, for Standard OMOG, but not for Thin OMOG. This interference, or undershoot is due in part to the low difference in reflectivity and phase between the quartz and the attenuator on the Standard OMOG substrate. This difference is more than five times greater for the Thin OMOG attenuator. The primary focus of this paper is on the characterization of thin OMOG relative to the interaction between attenuator reflectivity, image quality, database modeling and tool calibrations as they relate to mask inspectability and defect sensitivity. This paper will also address the changes required to compensate for the loss of sensitivity induced by the introduction of the thin OMOG absorber.

By the development of double exposure technique and the EUV lithography the pattern placement error of photomask is interested because of its impact on size and position of wafer pattern. Among various sources to induce the pattern placement error, we have focused on the resist charging effect and shown that the resist charging effect generates pattern position error and CD variation. Based on experiment and simulation, we present quantitatively the dependence of position error on pattern density, pattern shape, and writing order. Furthermore, we have discussed the model to describe the charging effect and its agreement with experiment, and correction method to remove the resist charging effect.

We report our development of fogging effect correction method aimed for EBM-8000, our newest series of EB mask writers for mask production of 22nm half-pitch generation and for mask development of 16nm half-pitch generation. We refined the method of fogging effect correction by taking account of dose modulation for proximity effects correction and loading effect correction into fogging effect correction, greatly reducing theoretical error. Writing experiment has shown that our method based on the threshold dose model is effective, though deviation from the model is observed.

A new correction approach was developed to improve the process window of electron beam lithography and push its resolution at least one generation further using the same exposure tool. An efficient combination of dose and geometry modulation is implemented in the commercial data preparation software, called Inscale®, from Aselta Nanographics. Furthermore, the electron Resolution Improvement Feature (eRIF) is tested, which is based on the dose modulation and multiple-pass exposure, for not only overcoming the narrow resist process windows and disability of exposure tool but also more accurate correction of exposure data in the application of sub-35nm regime. Firstly, we are demonstrating the newly developed correction method through the comparison of its test exposure and the one with conventional dose modulation method. Secondly, the electron Resolution Improvement Feature is presented with the test application for complementary exposure and with the application of real design, specifically for sub-30nm nodes. Finally, we discuss the requirements of data preparation for the practical applications in e-beam lithography, especially for future technology nodes.

Based on a massively parallel beam writing strategy (BACUS 2010) a mask writer proof-of-concept tool was realized in 2011. The eMET (electron Mask Exposure Tool) POC column is designed to provide ca. 262-thousand (512 x 512) programmable beams of 50 keV energy and 20 nm or 10 nm beam size. The total beam current through the column is up to 1 μA. The eMET POC is equipped with a laser-interferometer controlled stage for exposure of one cm² test pattern fields on 6" mask blanks. Operating the eMET POC with a stencil plate, first exposure results are presented. The further eMET POC project plan and the roadmap for eMET Alpha, Beta and multi-generational HVM tools are outlined.

We evaluate the projection fidelity of the Cell Projection (CP) using the Multi column cell (MCC) proof of concept (POC) tool [1-6]. The CP technology is originally developed as a method for reducing the shot counts of E-beam lithography systems. However, the higher repeatability of the shape is expected because the fixed size CP mask openings are used for each pattern. In the process of writing patterns by E-beam, the pattern deformation is inevitable due to the beam blur, proximity effect, and beam shaping error. If the model of beam deformation is established, the correction for the pattern deformation by modifications of CP mask opening shape can be carried out instead of additional shots. As a result, the shot count will be reduced. In this paper, we focused on Corner Rounding (CR) and Line End Shortening (LES) as two-dimensional properties of pattern deformation. Two-dimensional deformation should be decomposed in two components. One is the deformation in the process of CP mask manufacturing, and another is the deformation in the exposure process by e-beam writer tool. CP mask has been manufactured, measured and analyzed by Toppan printing. And using the CP mask, the exposure process error is measured by Advantest. By comparing the results, we evaluate the net amount of CP deformation caused in exposure process. Finally we confirmed the two-dimensional deformation is predictable by blur length that is obtained by one-dimensional CD-dose curve analysis.

EUVL requires the use of reflective optics including a reflective mask. The mask consists of an absorber layer pattern on top of a reflecting multilayer, tuned for 13.53 nm. The EUVL mask is a complex optical element with many parameters contributing the final wafer image quality. Specifically, the oblique incidence of light, in combination with the small ratio of wavelength to mask topography, causes a number of effects which are unique to EUV, such as an HV CD offset. These so-called shadowing effects can be corrected by means of OPC, but also need to be considered in the mask stack design. In this paper we will present an overview of the mask contributors to imaging performance at the 27 nm node and below, such as CD uniformity, multilayer and absorber stack composition, thickness and reflectivity. We will consider basic OPC and resulting MEEF and contrast. These parameters will be reviewed in the context of real-life scanner parameters both for the NXE:3100 and NXE:3300 system configurations. The predictions will be compared to exposure results on NXE:3100 tools, with NA=0.25 for different masks. Using this comparison we will extrapolate the predictions to NXE:3300, with NA=0.33. Based on the lithographic investigation, expected requirements for EUV mask parameters will be proposed for 22 nm node EUV lithography, to provide guidance for mask manufacturers to support the introduction of EUV High Volume Manufacturing.

Bit patterned media (BPM) for magnetic recording has emerged as a promising technology to deliver thermally stable magnetic storage at densities beyond 1Tb/in². Insertion of BPM into hard disk drives will require the introduction of nanoimprint lithography and other nanofabrication processes for the first time. In this work, we focus on nanoimprint and nanofabrication challenges that are being overcome in order to produce patterned media. Patterned media has created the need for new tools and processes, such as an advanced rotary e-beam lithography tool and block copolymer integration. The integration of block copolymer is through the use of a chemical contrast pattern on the substrate which guides the alignment of di-block copolymers. Most of the work on directed self assembly for patterned media applications has, until recently, concentrated on the formation of circular dot patterns in a hexagonal close packed lattice. However, interactions between the read head and media favor a bit aspect ratio (BAR) greater than one. This design constraint has motivated new approaches for using self-assembly to create suitable high-BAR master patterns and has implications for template fabrication.

The Jet and Flash Imprint Lithography (J-FILTM) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. It is anticipated that the lifetime of a single template (for patterned media) or mask (for semiconductor) will be on the order of 10⁴ - 10⁵imprints. This suggests that tens of thousands of templates/masks will be required to satisfy the needs of a manufacturing environment. Electron-beam patterning is too slow to feasibly deliver these volumes, but instead can provide a high quality "master" mask which can be replicated many times with an imprint lithography tool. This strategy has the capability to produce the required supply of "working" templates/masks. In this paper, we review the development of the mask form factor, imprint replication tools and the semiconductor mask replication process. A Perfecta^TM MR5000 mask replication tool has been developed specifically to pattern replica masks from an ebeam written master. Performance results, including image placement, critical dimension uniformity, and pattern transfer are covered in detail.

In order to achieve an economical design-to-mask (DTM) development cycle in the low k1 domain, designers, lithographers, and mask makers needed to move away from many sequentially isolated developmental activities onto one collaborative environment managed by a computational lithography platform that integrates their respective ecosystems. ^1,2 A successful development cycle used to be achievable by designers providing designs to lithographers, who then provided RET/OPC solutions to realize designs, but once k1 fell below a certain level, the lithographers could not provide solutions to realize some critical designs, which then required feedback to designers for further redesigns requiring further lithographic evaluation cycles. So collaboration and automations between lithographers and designers became necessary to reduce feedback loops and development cycle time. RET and design solutions also were impacted by mask making, and so mask maker's feedback on MRC and other constraints needed to be integrated for all three groups to achieve an economical DTM. As many lithographers attempted to print sub-80 nm pitches with 193 nm wavelength, it became necessary to use double patterning to achieve feature resolution. With the effective pitch doubling on each split layer, there could be significant increased design rule freedom for certain complex design situations. Using an integrated computational lithographic platform, one could find design space sweet spots that could further achieve optimal lithographic performance. In this paper, the optimization of design rules (DRD) for double pattern designs (~60 nm pitch) was explored with the mask maker's perspective. The experiment to be presented started with a 2x nm design set of clips. Each set of clips underwent size/width/space/pitch variations to generate a design space, and then each design space underwent SMO with an inverse lithography technology (ILT) engine using various mask MRC's and manhattan segmentations. The lithographic results were analyzed with respect to MRC and manhattan segmentation to show their impact on design space and mask solutions.

Source mask optimization (SMO) and double patterning technology (DPT) are considered key Resolution Enhancement Technique (RET) enablers for scaling 2x nodes and beyond design rules, using existing 193 nm ArF technology prior to EUV availability. SMO has been extensively shown to enlarge the process margin for critical layers in memory cells and test patterns; however the best SMO flow for a large random logic area up to full-chip application has been less explored. In this study, we investigated how the mask complexity in the source optimization impacts the final process window on a random logic layout after DPT, and proposed a new source optimization approach. Example used is a contact layer for 2x logic designs. The SMO source optimization is performed using the SRAM cells with different mask complexities. These optimized sources are then evaluated based on a large-area random logic layout after mask-only optimization. CD variation through process window is used as the metric for comparison. We found the best result is obtained when the source is optimized with the full flexibility of the source and mask with freeform SRAFs and minimal MRC constraints. The source optimized with this approach can reduce CD variation through process window in the random logic without increasing its mask complexity.

Organic electronics are gaining increasing interest and attention in electronic device fabrication due to cost advantages and low process manufacturing temperatures, which allow the use of mechanically-flexible polymeric substrates. Different patterning techniques for Organic Thin Film Transistors (OTFT) with sub μm channel length are currently under investigation like inkjet-printing, nanoimprint, optical- and e-beam lithography. This paper describes a new approach for OTFT fabrication by device patterning with Si stencil lithography. This high resolution shadow mask technique allows the parallel patterning of sub μm features without the use of photosensitive resists or chemical solvents, which could lead to a degradation of the sensitive organic semiconductor layer. At first the device pattern is etched into a thin Si membrane layer, creating design-specific sub μm features. Subsequent this stencil mask is aligned and clamped to the substrate and material is deposited through the stencil apertures forming the desired device pattern onto the substrate. By repeating this sequence with different deposition materials a classical top contact TFT architecture with a gate electrode, gate dielectric, organic semiconductor and source drain contacts can be achieved.

Technical problems with shrinking process node for semiconductor manufacturing has generated considerable interest in the use of multiple beams as an advance manufacturing technique in the context of direct write to mask / wafer. This paper examines the data preparation bottlenecks associated with this process. The various steps in the data preparation flow are described. Particular attention is paid to the large increase in data volume and the associated issues in processing power, transfer speed, storage requirements, and overall turn-around-time. Further, the use of commercial graphic processing units (GPUs) is examined as a possible solution to some of these issues and results of tests conducted as part of the MAGIC (MAskless lithoGraphy for IC manufacturing) initiative are summarized.

We have reported the first part of the work in 2009 BACUS meeting [1], using primarily SEM mask defect images as input. This paper is the extension of that work using mask optical inspection images with a new image process algorithm. Simulation has been widely used in overall lithography process, called computational lithography, as an effective way for cost and time reduction. As the industry moves towards 45nm and 32nm technology nodes in production, the mask inspection, with increased sensitivity and shrinking critical defect size, catches more and more nuisance and false defects. Increased defect counts pose great challenges in the post inspection defect classification and disposition: which defects are real defects, and among the real defects, which defects should be repaired and how to verify the post-repair defects. In this paper, we report simulation mask defect printability check and disposition results extending beyond SEM mask defect images [1] into optical inspection mask defects images to demonstrate cost and time reduction by simulation in mask defect management area. A new algorithm has been developed in the software tool to convert optical inspection mask defect images into "pseudo-defect" polygons in GDS format. Then, the converted defect polygons were filled with the correct tone to form mask patterns and were merged back into the original design GDS. With lithography process model, the resist contour of area of interest (AOI-the area surrounding a mask defect) can be simulated. If such complicated model is not available, a simple optical model can be used to get aerial image intensity of AOI. With build-in contour analysis functions, the software can easily compare the contour (or intensity) differences between real mask (with defect) and normal mask (without defect). With user provided judging criteria, software can be easily disposition the defect based on contour comparison. The software has been tested and adapted for production use. We will present some accuracy test results against AIMS tool or wafer CDs in defect printability check.

According to the ITRS roadmap, mask defects are among the top technical challenges to introduce extreme ultraviolet (EUV) lithography into production. Making a multilayer defect-free extreme ultraviolet (EUV) blank is not possible today, and is unlikely to happen in the next few years. This means that EUV must work with multilayer defects present on the mask. The method proposed by Luminescent is to compensate effects of multilayer defects on images by modifying the absorber patterns. The effect of a multilayer defect is to distort the images of adjacent absorber patterns. Although the defect cannot be repaired, the images may be restored to their desired targets by changing the absorber patterns. This method was first introduced in our paper at BACUS 2010, which described a simple pixel-based compensation algorithm using a fast multilayer model. The fast model made it possible to complete the compensation calculations in seconds, instead of days or weeks required for rigorous Finite Domain Time Difference (FDTD) simulations. Our SPIE 2011 paper introduced an advanced compensation algorithm using the Level Set Method for 2D absorber patterns. In this paper the method is extended to consider process window, and allow repair tool constraints, such as permitting etching but not deposition. The multilayer defect growth model is also enhanced so that the multilayer defect can be "inverted", or recovered from the top layer profile using a calibrated model.

According to the ITRS Roadmap, the EUV mask requirement for 2X nm technology node is detection of defect size of 20 nm. The history of optical mask inspection tools involves continuous efforts to realize higher resolution and higher throughput. In terms of productivity, considering resolution, throughput and cost, we studied the capability of EUV light inspection and Electron Beam (EB) inspection, using Scanning Electron Microscope (SEM), including prolongation of the conventional optical inspection. As a result of our study, the solution we propose is EB inspection using Projection Electron Microscope (PEM) technique and an image acquisition technique to acquire inspection images with Time Delay Integration (TDI) sensor while the stage is continually moving. We have developed an EUV mask inspection tool, EBeyeM, whole design concept includes these techniques. EBeyeM for 2X nm technology node has the following targets, for inspection sensitivity, defects whose size is 20 nm must be detected and, for throughput, inspection time for particle and pattern inspection mode must be less than 2 hours and 13 hours in 100 mm square, respectively. Performance of the proto-type EBeyeM was reported. EBeyeM for 2X nm technology node was remodeled in light of the correlation between Signal to Noise Ratio (SNR) and defect sensitivity for the proto-type EBeyeM. The principal remodeling points were increase of the number of incident electrons to TDI sensor by increasing beam current for illuminating optics and realization of smaller pixel size for imaging optics. This report presents the performance of the remodeled EBeyeM (=EBeyeM for 2X nm) and compares it with that of the proto-type EBeyeM. Performances of image quality, inspection sensitivity and throughput reveal that the EBeyeM for 2X nm is improved. The current performance of the EBeyeM for 2X nm is inspection sensitivity of 20 nm order for both pattern and particle inspection mode, and throughput is 2 hours in 100 mm square for particle inspection mode.

EUVL lithography using high resolution step and scan systems operating at 13.5nm is being inserted in leading edge production lines for memory and logic devices. These tools use mirror optics and either laser produced plasma (LPP) or discharge produced plasma (DPP) sources along with reflective reduction masks to image circuit features. These tools show their capability to meet the challenging device requirements for imaging and overlay. Next generation scanners with resolution and overlay capability to produce 1X nm (10 nm class) memory and logic devices are in preparation. Challenges remain for EUVL, the principal of which are increasing source power enabling high productivity, building a volume mask business encouraging rapid learning cycles, and improving resist performance so it is capable of sub 20nm resolution.

Reticle process of record (POR) sometimes needs fine tuning for some reasons such as multiple layer process, better critical dimension uniformity (CDU) or new etch chamber. The sidewall angle and corner rounding will be varied due to the reticle processing tuned comparing to previous POR. However, because the reticle critical dimension (CD) measurement is based on middle side lobe measurement or other algorithm, the reticle CD cannot reflect the changes of reticle sidewall angle and corner rounding variation which are critical for 65nm node and below. Each of the scanner, wafer process, reticle and metrology tool contributes to the intra-field wafer CD. Normally, the reticle contribution to the wafer CDU should be as small as possible, that is less than 33%. By averaging all wafer CD of individual features to obtain a wafer CD reference independent of feature location and wafer die, the correlation of wafer measurement to target (MTT) and reticle MTT can be obtained. The correlation can accurately qualify and monitor the tuning processing of reticle. We have manufactured two masks for active layer of 65nm tech node by different reticle process. One used the original POR process of active layer, while another used multi-layer-reticle (MLR) process. The correlations between wafer CDU and reticle CDU of these reticles are demonstrated for both isolated and dense features in vertical and horizontal direction, respectively. Similar experiments were implemented and the correlations for both dense and isolated structures are demonstrated as well, for two different POR process for first metal layer of 40nm tech node. Referring to the wafer and reticle MTT correlation, the contribution of reticle CDU to wafer CDU can be used as an evaluation methodology for reticle processing. The wafer and reticle CDU correlations for 45nm node poly and contact layers POR process are also demonstrated.

Nano-Imprint Lithography (NIL) is considered a promising alternative to optical lithography for technology nodes at 22nm hp and beyond. Compared to other advanced and complex lithography methods, NIL processing is simple and inexpensive making it a widely accepted technology for pattern media and a potential cost effective alternative for CMOS applications. During the NIL process, the template comes into direct contact with the resist on the substrate and consequently template cleanliness plays a decisive role in imprinted substrate quality. Furthermore, if the template has any form of a defect such as resist residue, stains, particles, surface scratches, chipping and bumping etc. it can lead to poor quality imprints, low yield and throughput decreases. The latest ITRS roadmap has stringent CD, CD uniformity, surface roughness and defect control requirements for NIL templates. Any template cleaning process that is adopted must be able to remove defects while maintaining the critical parameters outlined by the ITRS. Aggressive chemistries (such as NH4OH or SC1 (NH₄OH+H₂O₂+DI) and strong physical force treatments (such as MegaSonic & Binary Sprays) may cause damage to the template if not optimized. This paper presents the cleaning chemical effects on template surface roughness and CD at varying concentrations. The effect of physical force cleaning on fragile and sensitive pattern features is also presented. Particle & imprint resist removal efficacy at different process conditions is compared.

Any cleaning technology for state-of-the-art photo masks requires that pattern damage does not occur and optical characteristics do not change. Particularly with EUV masks, an important challenge is to suppress/prevent changes to the optical characteristics of ruthenium (Ru) film that generates when resist is removed (separated). This report illustrates a model explaining why optical characteristics change when conventional resist removal (separation) technologies are used on EUV mask. It also proposes a new resist removal technology that allows resist to be removed without any optical damage to Ru films.

Extreme Ultraviolet Lithography (EUVL) is the most promising solution for technology nodes 16nm (hp) and below. However, several unique EUV mask challenges must be resolved for a successful launch of the technology into the market. Uncontrolled introduction of particles and/or contamination into the EUV scanner significantly increases the risk for device yield loss and potentially scanner down-time. With the absence of a pellicle to protect the surface of the EUV mask, a zero particle adder regime between final clean and the point-of-exposure is critical for the active areas of the mask. A Dual Pod concept for handling EUV masks had been proposed by the industry as means to minimize the risk of mask contamination during transport and storage. SuSS-HamaTech introduces MaskTrackPro InSync as a fully automated solution for the handling of EUV masks in and out of this Dual Pod System and therefore constitutes an interface between various tools inside the Fab. The intrinsic cleanliness of each individual handling and storage step of the inner shell (EIP) of this Dual Pod and the EUV mask inside the InSync Tool has been investigated to confirm the capability for minimizing the risk of cross-contamination. An Entegris Dual Pod EUV-1000A-A110 has been used for the qualification. The particle detection for the qualification procedure was executed with the TNO's RapidNano Particle Scanner, qualified for particle sizes down to 50nm (PSL equivalent). It has been shown that the target specification of < 2 particles @ 60nm per 25 cycles has been achieved. In case where added particles were measured, the EIP has been identified as a potential root cause for Ni particle generation. Any direct Ni-Al contact has to be avoided to mitigate the risk of material abrasion.

With the market introduction of the NXE:3100, Extreme Ultra Violet Lithography (EUVL) enters a new stage. Now infrastructure in the wafer fabs must be prepared for new processes and new materials. Especially the infrastructure for masks poses a challenge. Because of the absence of a pellicle reticle front sides are exceptionally vulnerable to particles. It was also shown that particles on the backside of a reticle may cause tool down time. These effects set extreme requirements to the cleanliness level of the fab infrastructure for EUV masks. The cost of EUV masks justifies the use of equipment that is qualified on particle cleanliness. Until now equipment qualification on particle cleanliness have not been carried out with statistically based qualification procedures. Since we are dealing with extreme clean equipment the number of observed particles is expected to be very low. These particle levels can only be measured by repetitively cycling a mask substrate in the equipment. Recent work in the EUV AD-tool presents data on added particles during load/unload cycles, reported as number of Particles per Reticle Pass (PRP). In the interpretation of the data, variation by deposition statistics is not taken into account. In measurements with low numbers of added particles the standard deviation in PRP number can be large. An additional issue is that particles which are added in the routing outside the equipment may have a large impact on the testing result. The number mismatch between a single handling step outside the tool and the multiple cycling in the equipment makes accuracy of measurements rather complex. The low number of expected particles, the large variation in results and the combined effect of added particles inside and outside the equipment justifies putting good effort in making a test plan. Without a proper statistical background, tests may not be suitable for proving that equipment qualifies for the limiting cleanliness levels. Other risks are that a test may requires an unrealistic high testing effort or that equipment can only pass for a test when it meets unrealistic high cleanliness levels. TNO developed a testing model which enables setting up a qualification test on particle cleanliness for EUV mask infrastructure. It is based on particle deposition models with a Poisson statistics and an acceptance sampling test method. The test model combines the single contribution of the routing outside the equipment and contribution of multiple cycling in the equipment. This model enables designing a test with minimal testing effort that proves that equipment meets a required cleanliness level. Furthermore, it gives insight in other equipment requirements on reliability.

With EUV Lithography systems shipping, the requirements for highly reliable EUV sources for mask inspection and resist outgassing are becoming better defined, and more urgent. The sources needed for metrology applications are very different than that needed for lithography; brightness (not power) is the key requirement. Suppliers for HVM EUV sources have all resources working on high power and have not entered the smaller market for metrology. Energetiq Technology has been shipping the EQ-10 Electrodeless Z-pinch^TM light source since 19951. The source is currently being used for metrology, mask inspection, and resist development2-4. These applications require especially stable performance in both output power and plasma size and position. Over the last 6 years Energetiq has made many source modifications which have included better thermal management to increase the brightness and power of the source. We now have introduced a new source that will meet requirements of some of the mask metrology first generation tools; this source will be reviewed.

Requirements coming from the customer, as well as internal needs of improvements consequent to the increasing complexity of the layout of the newest devices, lead to the necessity of exploring all the potential improvements achievable at the mask manufacturing inspection process. A key point to manage for the better DB inspections is that of being able to achieve a proper matching between the images to be compared, tasks which is accomplished by the tool architecture by means of a pre-swath calibration process on which the quality of the focus is playing a relevant role. From here the decision to focus on this parameter aiming of working out and evaluate a different approach to be used to set the scanning focus on the inspection tool moving from the vendor theory based on the edge speed on a specific test plate to a new one based on intensity measurements into specific features on a purposely designed test vehicle. A matter of relevant importance for mask makers, either for the smoothness of the inspection process or for the homogeneity of the quality of the products being delivered, but on which any tool vendor likes providing official commitments, is that of correlating the overall performance of similar tools. This was accomplished with the new approach with two different tools achieving optical images with similar grey scale distributions into the most critical features. Moreover, the improvement of the matching of the images being compared allows extending the usage of the tool for products for which the complexity of the layout forced the inspection with different pixels or with more advanced tools, with a positive impact either on costs or on the cycle time of the masks being delivered. A careful assessment-verification of the shadowing limitation induced by the frame of the pellicle was another task successfully carried out with the new methodology, with some improvement regarding the inspectable area. The extended its usage the wider the field of application will become, but few advantages can be appreciated since the beginning: the focus will be set on a production like layer, its choice will not be depending on a human decision, it will be a simple, fast and reliable process runable at any time and at any operating level.

EUV lithography is expected to begin production in 2014. Production of successful EUV photomasks requires patterned mask inspection (PMI). The ultimate PMI tool is expected to utilize actinic (EUV) illumination. Development of such a tool is expected to require three years after funding. Current test EUV masks, such as 22 nm, can be inspected using 193 nm wavelength deep UV (DUV) inspection tools similar to those currently being used for DUV masks. The DUV inspection tools may be extended for the 16 nm node. However EUV production is expected to start with 11 nm node masks which cannot be inspected with proposed DUV inspection tools. Therefore E-beam inspection (EBI) is discussed as the interim PMI method. EBI has the advantage of high resolution and the disadvantages of low inspection speed and relative insensitivity to ML defects (in the multi-layer material). EBI inspection speed is limited by the pixel size, pixel capture rate and the number of electron columns. The pixel rate is limited by the detector time-resolution, the beam current, and the detection efficiency. Technical improvements in beam focus, secondary electron detection, and defect detection and analysis provide good performance for 22 nm node masks. We discuss the advances and show that performance can be extrapolated for 16 and 11 nm node patterned mask inspections. We present sensitivity and false-defect frequency results of using the Holon EBI tool on 22 nm test masks and a roadmap for extending its operation for use on 16 and 11 nm node masks for inspections requiring 2-5 hours per mask.

A number of new technologies and processes have been developed for deep ultraviolet (DUV) wavelength and femtosecond pulsed laser repair of photomasks. These advances have been shown to improve and extend the repair of both pelliclized and non-pellicilized photomasks for both hard and soft (or nano-particle) in exhaustive testing at the factory and the end-user site. However, even the best testing is only a simulation of what a repair tool will see when brought into full production. The purpose of this work is to review some of the knowledge and experience gained in bringing the repair processes defined with manufactured defects to the more variable defects encountered in the real world. The impact of the repair technology on increases in mask house throughput and decrease in costs will also be compared to other (another laser and an advanced FIB) repair tools.

A number of new RET's have come to significant adoption in advanced lithography recently, extending technology trends that have allowed the use of 193 nm wavelengths for nodes well beyond their intended limits. These enhancement technologies include Computational Lithography (CL) techniques such as Source-Mask Optimization (SMO), and use of innovative materials such as Opaque MoSi on Glass (OMOG). These new techniques are of particular focus for examination of their applicability to nanomachining photomask repair. Historically comparative repair results are shown for the OMOG absorbers which can contain a multi-layer potentially in combination with quartz over-etching for phase correction. The implementation of nanomachining for CL/SMO photomasks encompasses a larger set of new technologies introduced in a nanomachining repair tool. These include tip shape de-convolution for improved accuracy and reproducibility of large complex patterns - many of which are non-orthogonal, and automated import of mask design data to seed the repair polygon for a pattern which may be unique on the entire mask area (i.e. no pattern reference).

The mask inspection and review process is a vital part of mask preparation technology and consumes a significant amount of mask preparation time. As the patterns on a mask become smaller and more complex, the need for a highly precise mask inspection system with a high detection sensitivity and low number of false defects becomes greater. A low number of false defects is desirable as the results of the mask inspection are typically reviewed manually by an operator in the mask shop. However, due to various reasons, the probable mask defects identified by any mask inspection machine could include significant number of false defects. The false defects could be due to registration or focus errors between the defect and reference images (Die-to-Die or D2D comparison), CCD (Charge-coupled device) errors in the camera, noisy pixels etc. These false defects cannot be ignored and require the operator to review them manually before classifying them as false defects. This takes valuable time and effort of the mask inspector and increases the turn-around-time of mask inspection. We propose a software tool which automatically detects most of the false defects generated due to registration and CCD errors in the mask inspection system. It is quite common to find several thousands of defects (real as well as false defects) during mask inspection. We have observed that significant percentage of these false defects are due to registration and CCD errors in defect and reference images during D2D inspection. Automatic detection of registration and CCD errors requires image processing to be done on the defect images. This process is typically, time consuming. However, image processing algorithms are well suited for parallelization. We explore the use of GPUs to speed up the false defect detection process by analyzing the defects in parallel on multiple cores of a GPU. In addition, GPUs are inexpensive, readily available and can be plugged in to any desktop computer which makes it easier to adopt. The proposed GPU based parallel false defect detection feature is integrated into Mask Defect Analysis tool - NxDAT¹.

Extreme ultraviolet (EUV) e-beam patterned mask inspection (EBPMI) has been proposed by Applied Materials as a cost-effective solution for high volume manufacturing (HVM) in mask shops and fabs. Electron beam inspection technology is currently available for wafers. A recent publication described a successful sensitivity study of EUVs mask using a technology demonstration platform. Here we present a new study using extreme e-beam conditions to show the feasibility of using EBPMI in HVM. We examine potential changes in the reflectivity at the EUV wavelength after exposure to high e-beam currents, demonstrating that reflectivity does not change due to e-beam scanning. We therefore conclude that under the conditions tested, which include typical as well as extreme conditions, there is no evidence of mask damage.

In order to maintain manageable process windows, mask shapes at the 20nm technology node and below become so complex that mask write times reach 40 hours or might not be writeable at all since the extrapolated write time reaches 80 hours. The recently introduced Model Based Mask Data Preparation (MB-MDP) technique is able to reduce shot count and therefore mask write time by using overlapping shots. Depending on the amount of shot count reduction the contour of the mask shapes is changed leading to the question how the mask contour influences wafer performance. This paper investigates the tradeoff between mask shot count reduction using MB-MDP and wafer performance using lithography simulation. A typical Source-Mask-Optimization (SMO) result for a 20nm technology will be used as an example.

The extension of 193nm exposure wavelength to smaller nodes continues the trend of increased data complexity and subsequently longer mask writing times. We review the data preparation steps post tapeout, how they influence shot count as the main driver for mask writing time and techniques to reduce that impact. The paper discusses the application of resolution enhancements and layout simplification techniques; the fracture step and optimization methods; mask writing and novel ideas for shot count reduction. The paper will describe and compare the following techniques: optimized fracture, pre-fracture jog alignment, generalization of shot definition (L-shot), multi-resolution writing, optimized-based fracture, and optimized OPC output. The comparison of shot count reduction techniques will consider the impact of changes to the current state of the art using the following criteria: computational effort, CD control on the mask, mask rule compliance for manufacturing and inspection, and the software and hardware changes required to achieve the mask write time reduction. The paper will introduce the concepts and present some data preparation results based on process correction and fracturing tools.

The demand for aggressive image placement accuracy for each generation is being increasingly accelerated by DPT deployment. The method of the correction with the scanner is in effect devised by obtaining the CD and IP maps of each mask after the mask pattern is drawn, We are developing a technology that generates CD and IP maps for each mask from the image data of inspection equipment with the ultimate goal of "in-die overlay improvement" optimizing scanner as well as writer performances. We have reported in-die CD and registration metrology capability of mask inspection equipment. However existing inspection machines, which are already in use, do not have such features to perform this function, as they are not designed for such purpose. We are developing a method to improve measurement accuracy by incorporating registration mark data obtained by conventional metrology tool, and will report the result of evaluation of this method.

As technology move forward, the layer-to-layer overlay requirement becomes a serious challenge on wafer process. It also causes more difficult overlay control on mask process. Hence, the mask image placement has been required tighter and tighter. Currently, most of mask houses measure image placement before pellicle mounting. However, foundries always exposes wafer by post pellicle mask to avoid particle falling on image plane to cause defects on wafer. The mask image placement before pellicle mounting can't fully represent the real mask image placement during wafer process. Therefore, we need to evaluate the image influence of image placement on the mask after pellicle mounting. Some testing was checked on our production masks. We find that the image placement is difference between post pellicle and before pellicle. It means that the registration had been changed after pellicle mounting. The result outstrips our suspect. Therefore, reducing the influence of image placement after pellicle mounting becomes more and more important. We found that the image placement of through pellicle should be impacted by some factors. We suppose that these factors should be pellicle frame related. We cooperate with mask vendor (HOYA) to evaluate these factors and reveal the improvement result in this paper. Finally, we improve around 50% image placement difference between post pellicle and before pellicle.

Nano-Imprint Lithography and a mold, mold replication from an EB master mold as well, those are essential for a large-scale production of patterned media. In nano-imprinting, since it is contact printing, a higher separation force might cause damages to the master and imprinting tool, degradation in pattern quality as well. Those difficulties also work to retard continuous imprinting for the mold replication. Then, we focused on release materials characterization and selection to facilitate clean separation between cured resist and the master. This paper describes a novel release material, and continuous nano-imprinting results with it for replica mold fabrication from an EB master for the patterned media application.

As lithography moves into lower k₁ imaging, traditional illumination "source" shapes may perform marginally in resolving complex layouts. Subsequently hot-spots or warm-spots can result, leading to yield loss in production. Typically, lithographers solve such problems by modifying the local layout instead of optimizing the DOE (diffractive optical element) illumination shape. FlexRay^TM can easily implement freeform source shapes and allows a high degree of freedom in source optimization. Therefore, it becomes practical to use pixelated freeform sources to resolve hot spots or warm spots. In this paper, we investigate the use of freeform source optimization (SO) on a critical dynamic random access memory (DRAM) layer with warm spots to verify the effectiveness of a SO only flow using Tachyon SMO. In order to improve the warm spots without changing baseline performance for other patterns, we optimized not only the warm spot patterns of concern but also the critical reference patterns. Since the optimization minimizes EPE (edge placement error) and maximizes imaging quality for all enclosed patterns, the final optimized source shape performs similar to the baseline source for the base patterns while improving the performance of the warm spot pattern areas. Although the SO source is similar in shape to the baseline source, the optimized source provides enhanced depth of focus (DoF) for all warm spot patterns without suffering degradation in the normalized image log-slope (NILS) performance. Evaluation of the optimized SO source shows no obvious negative impact on modeled CDs across an array of L/S pattern combinations which cover all the pitches appearing in the periphery. Finally, the optimized source is demonstrated using ASML's FlexRay^TM for on-wafer evaluation. According to the observations from on-wafer experiments, consistent results to simulation are verified. Overall DoF for the identified warm spot patterns is definitely improved and no obvious pattern shape changes are found, as well. From the positive demonstration in simulation and on-wafer verification, the vast flexibility of the freeform source enables the SO flow with more powerful capability to improve local hot spot or warm spot problems without negatively impacting the other patterns.

Double Patterning is the most promising lithography solution for 22 nm technology node and beyond. It can both increase the pitch density and print intricate 2D patterns reliably, far beyond the capabilities of the conventional Double Exposure methods. Recently, a double exposure method in a single photoresist layer using image reversal DESIR has been proposed which matches the printing capabilities of the double patterning technology while using only one photoresist layer, resulting in a significant process simplification. In general, layout decomposition poses a major obstacle in terms of layout complexity, layout verification overhead, and mask decomposability design related issues. Here, a layout decomposition method and mask selection algorithms for the DESIR approach that can be easily implemented in any mask design tool are proposed. The method is distinctly different from extant layout decomposition techniques because of the intricate photoresist properties subject to several exposures and an intervening critical image reversal baking step. The challenge in the layout decomposition is that the exposure seen by each area before and after the reversal bake determines the solubility of the resist. This circumstance constitutes a welcomed benefit of optimum pattern printability by using an internal corner counting algorithm.

Self-aligned double patterning (SADP) lithography is a novel lithography technology which has the capability to define critical dimension (CD) using one single exposure, therefore holding a great opportunity for the next generation lithography process for the overlay mitigation. However, a necessary design manufacturing co-optimization step - the non-decomposability position detection (hot spot detection) - is still immature. In this paper, targeting the hot spot detection difficulties in SADP process, we first revisit out previous ILP-based SADP decomposition algorithm and provide an extended ILP-based hot spot detection without any preconditions on the design. Then, with some simple requirement that is commonly seen in 2D random layout, we further provided a graph based hot spot detection for an efficient hot spot detection. From the Nangate standard cell library, our experiment validates the hot spot detection process and demonstrates an SADP friendly design tyle is necessary for the upcoming 14nm technology node.

The 28nm technology node is extremely challenging for the production of large chips with very aggressive design rules. For the 1x-Metal layers especially, it has been observed that some design configurations known as hotspots have very limited lithographic process window. They have generally complex bidimensional geometries that make them highly sensitive to any process change and particularly to focus variation or mask error. The first purpose of this study is to present an original methodology to characterize, with good statistics, the hotspots after lithography. The principle is to stack many SEM pictures of the same hotspot, repeated on the wafer, to improve the image signal-to-noise ratio and to average uncontrolled sources of CD variation. With such high quality images it is then possible to extract contours of high accuracy. The second scope of this work is to take advantage of the extracted contours to derive many CD measured preferentially along the hotspot critical sections. The main contributors to CD variation are identified by analyzing the CD of hotspots processed under different experimental conditions like intra-field locations, mask sizing or focus changes.

Some chip manufacturing steps lead to non-negligible process variation at wafer level. Typically, chemomechanical planarization, known as CMP, is a nonhomogeneous process and thickness variations can be measured depending on the distance from a specific die to the wafer center. These variations have an impact on chip performances and thus on the final yield. This effect may be amplified by the fact that thickness variations on processed wafers introduce focus issues during later photo-lithography steps. Original chip layouts are modified by inserting dummies to correct thickness variation issues due to CMP, but these correction are based on models only depending on average values. In this paper, we propose a methodology to replace a single instance of the field written on the mask by multiple instances of this field as commonly used for Multi Layer Reticles. In the described methodology, each field of a same mask does not consist in different layers of the same chip, but of an optimized image of the same layer of the chip.

A dynamic feedback controller for Optical Proximity Correction (OPC) in a random logic layout using ArF immersion Lithography is presented. The OPC convergence, characterized by edge placement error (EPE), is subjected to optimization using optical and resist effects described by calibrated models (Calibre® nmOPC simulation platform). By memorizing the EPE and Displacement of each fragment from the preceding OPC iteration, a dynamic feedback controller scheme is implemented to achieve OPC convergence in fewer iterations. The OPC feedback factor is calculated for each individual fragment taking care of the cross-MEEF (mask error enhancement factor) effects. Due to the very limited additional computational effort and memory consumption, the dynamic feedback controller reduces the overall run time of the OPC compared to a conventional constant feedback factor scheme. In this paper, the dynamic feedback factor algorithm and its implementation, as well as testing results for a random logic layout, are compared and discussed with respect to OPC convergence and performance.

The thickness for a material to be used for photolithography process is typically monitored on test wafers with a completely flat surface. Therefore material's specification is limited to thickness uniformity, reflectance, refractive indexes and chemical properties. NVM embedded IC's integrating a variety of devices within the same chip may lead to challenging topography at gate level. Tight control of transistors CD, coherent with model based OPC treatments precision, is hard to achieve in circuitry regions with small surface before resist coating. The proposed model is based on reflectance increase in areas where observed CD is small with respect to the target. The observed root cause of CD loss is linked with materials' behavior in the proximity of edges of silicon structures and with the overall thickness reduction when the blocks become small. A set of test patterns is defined and substrates are prepared with planarizing and conformal BARC's to quantify the influence of topography on the CD. The geometries provide a good sampling in terms surface. After lithography, the dimensional effects are quantified by top view SEM. A model describing materials thinning can be computed from CD behavior data in the case of inorganic BARC. The study shows the limitations of both types of BARC's and suggests that Optical Proximity Correction could be used to compensate the effects of topography. Some recommendations are made in order to fulfill 65nm and smaller technology nodes' requirements. Several components of the study can be combined to master topography effects in complex process flows.

As the demand for taking Source Mask Optimization (SMO) technology to the full-chip level is increasing, the development of a flow that overcomes the limitations which hinder this technology's moving forward to the production level is a priority for Litho-Engineers. The aim of this work is to discuss advantages of using a comprehensive novel SMO flow that outperforms conventional techniques in areas of high capacity simulations, resist modeling and the production of a final manufacturable mask. We show results that indicate the importance of adding large number of patterns to the SMO exploration space, as well as taking into account resist effects during the optimization process and how this flow incorporates the final mask as a production solution. The high capacity of this flow increases the number of patterns and their area by a factor of 10 compared to other SMO techniques. The average process variability band is improved up to 30% compared to the traditional lithography flows.

Litho-etch-litho-etch (LELE) double patterning lithography (DPL) is a strong candidate for BEOL patterning at the 20nm logic half-node (sub-80nm pitch). In double patterning lithography, layout pattern features must be assigned opposite colors if their spacing is less than the minimum coloring spacing. However, complex layouts usually have features that are separated by less than the minimum coloring spacing for any coloring assignment. To resolve the minimum coloring spacing constraint, a pattern feature (polygon) can be split into two different-color segments, introducing a stitch at the splitting location. Although many DPL layout decomposition heuristics have been proposed, the impact of stitches on circuit performance is not clearly analyzed. In this work, we study the impact of stitches on BEOL electrical performance based on analytical RC equations. Our studies with 45nm (commercial) and 22nm (ITRS) technology parameters show that (1) optimal stitching location can reduce delay variation by 5%, and (2) introducing redundant stitches (i.e., splitting an interconnect segment intentionally) can potentially reduce circuit delay variation.

Improvements in compact lithography models and compute resources have allowed EDA suppliers to keep up with the accuracy and turnaround time (TAT) requirements for each new technology node. Compact lithography models are derived from the Hopkins method to calculate the image at the wafer. They consist of the pre-calculated optical kernel set that includes properties of projection and source optics as well as resist effects. The image at the wafer is formed by the convolution of optical kernel set with the mask transmission. The compact model is used for optical proximity correction (OPC) and lithography rule checking (LRC) due to its excellent turnaround time in full chip applications. Leading edge technology nodes, however, are inherently more sensitive to process variation and typically contain more low contrast areas, sometimes resulting in marginal hotspots. In these localized areas, it is desirable to have access to more predictive first principle lithography simulation. The Abbe method for lithography simulation includes full 3D resist models that solves from first principles the reaction/diffusion equation of the post exposure bake to provide the highest accuracy. These rigorous models have the ability to provide added insight into 3D developed profile in resist at the wafer level to assist in the application of OPC and disposition of hotspots found by LRC using compact models. This paper will explore the benefits of a tightly integrated rigorous lithography simulation during LRC hotspot detection step of the post OPC flow. Multiple user flows will be addressed along with methods for automating the flows to maximize the imaging predictability where needed while keeping the impact to turn around time to a minimum.

The ITRS roadmap¹ lists double patterning 193 nm immersion exposure with inverse lithography as the likely solution through the 22 nm half pitch generation. Three different patterns, scaled to 56 nm pitch, were explored using inverse lithography.^2,3 The patterns are a trim mask design adapted from Schenker, et al.⁴, a bit line design published by Pyo, et al.⁵ and a metal layer design published by Lucas, et al.⁶. A free form gray scale illuminator was determined for each pattern. Good results were obtained for the trim mask design with a process variation of less than 8 nm for 50 nm of defocus and MEEF less than 6. The bit line design had to be modified from the published version which increased the pattern area by 18.8%. For this pattern there was a maximum process variation of 11 nm for 50 nm of defocus and MEEF less than 14. The metal layer design had to be modified which increased the pattern area by 2.6%. With these changes there was a maximum process variation of 8.4 nm for 50 nm of defocus and MEEF less than 7.

Model Based Optical Proximity Correction (MB- OPC) is essential for the production of advanced Integrated Circuits (ICs). As the speed and functionality requirements of ICs production always require reducing the Critical Dimension (CD), the demand is continuously increasing for more accurate and representative OPC models. The current known best practice is to calibrate OPC models with measured test patterns. Test patterns are selected to represent the final designs to be printed in any specific technology that will use the OPC solution. The accuracy of the OPC models is critical to obtain the right product pattern dimension and consequently to the success of the IC production process. After building the OPC model, a model verification step is completed by the OPC modeling engineer to check the OPC model performance before using it in the IC production process. This model verification step is critical for selecting the best possible model that represents the lithography process. In this paper, we are proposing an additional technique for judging the accuracy and performance of the OPC model. The additional verification technique is to add on the test mask additional custom features specially designed in dimension and spacing in a way that they marginally print on the wafer. The accuracy of the OPC model is then tested by checking how the model predicts the printability of these additional structures.

Asahi Glass Company (AGC) has been developing the extreme ultra violet (EUV) lithography mask blank and polished substrate since 2003, including the developments of all essential materials and processes: the low thermal expansion material (LTEM), the material developments of the reflective, capping and absorber films, the process developments of the substrate polishing, cleaning, film deposition and resist film coating processes. In this paper, we present the current development status of the full-stack EUV mask blank and polished substrate which are the most suitable for the EUV lithography process development with EUV pre-production exposure tools. We report the development progress of the reflective multilayer-coated LTEM substrate by showing its critical performances with those of 2010 achievements, which include the substrate flatness, the EUV optical properties of the Mo/Si reflective layers and the defect of LTEM substrate and reflective layer. The performances of the Ta-based absorber and the resist films are explained as well to show the readiness of the EUV mask blank suitable for various kinds of process developments of the EUV lithography.

Through a series of experiments and simulation studies, this paper will explore the lithographic impact of absorber thickness choice on an EUV photomask and highlight the trade-offs that exist between thick and thin absorbers. Fundamentally, thinning the absorber modifies the intensity and phase of light reflected from the absorber while simultaneously decreasing in the influence of feature edge topography. The decision to deploy a thinner absorber depends on which imaging effect has a smaller impact after practical mitigation and correction strategies are employed. These effects and the ability to correct for them are investigated by evaluating the absorber thickness impact on lithographic imaging performance, stray light effects, topography effects, and CD variability. Although various tradeoffs are described, it is generally concluded that thinning the absorber thickness below around 68 nm is not recommended for a TaBN/TaBO absorber stack.

In the semiconductor technology using the 193nm ArF excimer laser, the problem of radiation damage on photomask becomes more serious. This phenomenon is regarded as serious issue for semiconductor device fabrication. Some approaches have been tried to prevent the radiation damage. One of reports indicates that the radiation damage can be reduced by using an exposure tool with ultra clean extreme dry air [1]. However, it is difficult to adopt dry air into all exposure tools due to high cost. In our previous work, two facts were ascertained; radiation damage is caused by MoSi film oxidation, and depends on MoSi film composition [2]. In this paper, radiation damage was tried to decrease by MoSi film modification of att. PSM. MoSi film composition for PSM is optimized in consideration of cleaning durability, mask defect repair and processability. The new PSM is named AID (Anti Irradiation Damage). Radiation damage of AID PSM can be improved by 40[%] from conventional PSM. Cleaning durability can be also improved by AID PSM. The other evaluation items such as CD performance, cross section, defect level and repair, are equal between the AID PSM and conventional one. Additionally, the lithography performances by simulation of AID PSM are equivalent with that of conventional PSM. Therefore, it can be expected that there is no difficulty in converting conventional PSM into AID PSM. From these evaluation results, development of AID PSM was completed, and preparation for production is now going.

ABF (Advanced Binary Film) developed by Hoya as a photomask for 32 (nm) and larger specifications provides excellent resistance to both mask cleaning and 193 (nm) excimer laser and thereby helps extend the lifetime of the mask itself compared to conventional photomasks and consequently reduces the semiconductor manufacturing cost [1,2,3]. Because ABF uses Ta-based films, which are different from Cr film or MoSi films commonly used for photomask, a new process is required for its etching technology. A patterning technology for ABF was established to perform the dry etching process for Ta-based films by using the knowledge gained from absorption layer etching for EUV mask that required the same Ta-film etching process [4]. Using the mask etching system ARES, which is manufactured by Shibaura Mechatronics, and its optimized etching process, a favorable CD (Critical Dimension) uniformity, a CD linearity and other etching characteristics were obtained in ABF patterning. Those results are reported here.

Critical aspect ratio induced pattern collapse has been a concern for lithography process engineers since before the 180 nm node. This has driven a steady reduction in photoresist thickness, as well as accelerated the introduction of hard mask materials and processes. There have been multiple studies and proposed models for the fundamental forces which lead to pattern collapse, with consensus being that differential capillary forces across opposing sides of a developed photoresist line during the water rinse/dry step are responsible for line bending. This line bending can lead to pattern deformation or complete substrate adhesion failure. Several process improvements, such as surfactant-laced final rinse, have been proposed to alter surface energies and increase the critical aspect ratio for collapse. The mechanical models which have been proposed to explain this phenomenon have all been effectively two-dimensional, characterizing the aspect ratio (Z/X) for an idealized pattern assumed to be semi-infinite in the Y dimension. While these models are very helpful for guiding materials/process understanding and improvement, they are not as helpful in predicting real random logic "hotspots": pattern locations most likely to fail through the manufacturing process window. This work proposes a framework for full-chip prediction of pattern collapse failure by use of a semi-empirical model and an efficient geometric checking engine. Idealized test patterns are studied initially, in order to reproduce behaviors commonly reported in the literature for semiinfinite Y patterns, and then more complex layout configurations are introduced. It is shown that full-chip pattern collapse can be efficiently and accurately predicted. Such a capability can prove valuable in setting design rules, and in refining RET solutions.

The impact of edge profile roughness of the absorber lines on an optical photomask has been studied by means of rigorous EMF simulation for the mask diffraction spectrum and subsequent imaging. Roughness has been modeled using two different approaches, a sinusoidal description and an algorithm known from literature based on Fourier transformation. The latter one allows one to arbitrarily create rough profiles and surfaces based on the three morphological parameters standard deviation σ, roughness exponent α, and correlation length ξ. A software interface for use of the generated profiles with the waveguide EMF solver of the Dr.LiTHO lithography simulation suite has been implemented. It was shown by means of image analysis and study of the resulting process windows that mask roughness is partially transferred to the aerial image. Isolated and dense features behave differently, leading i.a. to an iso-dense bias different to that of ideal lines. Process windows shift or even shrink in the presence of roughness, due to a certain smearing of the curves reducing the overall window. Tapered sidewalls can add to these effects in the same order of magnitude.

Best focus variation among different device features is one of the limiting factors to process window in semiconductor photolithography applications. Accurate prediction of best focus variation in full-chip optical proximity correction (OPC) and verifications is important in order to detect and mitigate the problem in design and post-design stages. In this work, the origin of best focus variation is first studied analytically by analyzing a simple but important imaging problem. It shows that phase difference between diffraction orders causes best focus shift. Then a rigorous simulation of mask diffraction further shows that the phase difference induced by 3D mask topography is non-zero and is a function of pattern and angle of incidence onto the mask. As a result, 3D mask models that can take into account oblique incidence effects are required in order to accurately predict best focus variations in full-chip applications. Tachyon M3D is a fast 3D mask model developed for full-chip OPC and verifications. Its accuracy in predicting best focus variation against measured wafer data is evaluated in this work. The results show very good correlation between M3D simulations and experiments.

Bimetallic grayscale photomasks contain two thin layers of metals (Bismuth/Indium or Tin/Indium), 15-300nm thick on transparent substrates. Laser exposure converts the films by thermal reaction into transparent alloy oxides. The Optical Density changes from ~3.0OD (unexposed) to <0.22OD (fully exposed), creating grayscale photomasks. With using a open loop direct-write raster-scan writing system with a CW Argon-ion laser, grayscale masks with 6-bit accuracy was achieved. To reduce mask nonuniformity, sensors added to the beam path before and after the mask turning the system to create a real-time OD and beam measurement feedback system. This feedback compensates for changes in film parameters: film thickness reducing the mask error to ±0.3 gray-levels, yielding to a potential 256 gray-level mask. This leaves nonuniformities due to the Gaussian shape still limits the accuracy. To remove these, a refractive field-mapping shaper was used to create a nearly flat-top power laser spot power distribution. The OD system also allows us to profile the grayscale levels in more detail after writing. A full 8-bit picture was written on a test mask with the feedback system showed significant improvement in the number of gray-levels. Some fluctuations were observed at the final pattern due to spaces between lines and nonuniformity of table speed. Some 3D test structures are created on the photoresist with the masks written with the feedback system to demonstrate the accuracy and grayscale abilities of the bimetallic thin-films

Reticles are contaminated during its lifetime and can catch particles as large as several tens of microns. Such defects on the backside of photomasks are usually considered as uncritical and thus do not receive much attention. Backside defects are out of focus by the mask thickness during wafer exposure and cannot be directly imaged on wafer. However, the shadow of the defects changes the local illumination of the mask patterns and may result in spatial variation of critical dimension (CD) on wafer depending on numerical aperture (NA) and pupil shape. There have been only a few investigations on printability of backside defects in the past, and no data are available for the most advanced technology nodes. Reticles are regularly inspected for particles on the glass side in the wafer fab but limits for acceptable defect size are based on estimations. Detection of non-acceptable particles causes exposed wafers being either delayed or reworked with impact on throughput and cost performance. It is therefore important to gain better understanding of critical sizes of backside defects and of appropriate detection capabilities. We have designed and manufactured a test mask with repeating patterns of 20nm, 28nm and 40nm technology node ranging from contact and line/space critical layers to non-critical implant layers. Programmed chrome defects of varying size are placed on the backside of the mask opposite to the repeating front side patterns in order to measure the spatial variation of transmission and wafer CD caused by the backside defects. The test mask was printed on a bare Silicon wafer and the size of printed features was measured by spatial sampling. Wafer CD variation for different backside defect sizes are demonstrated and compared for 28nm node first metal layer. Although the opaque chrome defects on the backside do not behave like real particles they aim on deriving a print threshold for backside particles based on actual wafer data. After such critical size of backside defects is obtained the reticle was also utilized to investigate the detection ability of backside defects by defect inspection of the reticle.