This PDF file contains the front matter associated with SPIE Proceedings Volume 7974, including the Title Page, Copyright information, Table of Contents, and the Conference Committee listing.

Traditional transistor scaling methods served our industry well for more than three decades until the early 1990s when leakage current and active power constraints threatened to end the continued improvements provided by Moore's Law. The end of the traditional scaling era ushered in the beginning of the innovation era. Process technology innovations such as strained silicon, high-k metal gate transistors, and copper + low-k interconnects have enabled continued performance improvements for scaled devices. Microprocessor design and architecture innovations such as multi-core designs combined with power gates were significant contributors to improved performance and improved power efficiency. Future computing products demand small form factors and long battery life that can be met through a combination of transistor innovation, System-on-Chip and System-in-Package integration techniques.

Layout pattern minimization has become a necessity at the 20nm technology node. Not only is it the only way to guarantee convergence for source mask optimization, having a well defined design space by limiting the total number of layout patterns, is the only way to ensure complete verification of design space during technology bring-up. In this paper we would reveal the details of PDF Solutions template and connector based layout design methodology that enables designers to achieve competitive layout density by limiting layout patterns. The use of this methodology enables a 25X pattern count reduction compared to the gridded logic layouts and is the only solution available that ensure pattern count saturation within a 40um x 40um random block of logic. Results on SMO compatibility have been highlighted by the collaborative work between ASML and PDF Solutions. In this paper we have discussed the development of a layout fabric developed for SMO and DPT compatibility, the definition of the base template and corresponding connector templates to provide the fabric constraints to designers and results highlighting the lithographic benefits of this approach. In effect, we have proposed a design solution that can provide a low-risk 20nm technology node enablement.

Static Random Access Memory (SRAM) cells use the smallest manufacturable device sizes in a given technology and hence see a highly pronounced random dopant effect. Moreover, SRAM cells are designed to satisfy conflicting read and write requirements. It makes SRAMs extremely vulnerable to failures due to lithographic variations. We propose a design centering approach for maximizing SRAM electrical yield under lithographic variation. The centering is obtained by applying small biases to the gate lengths of devices in the circuit. We refer to this process of enhancing electrical yield by changing the original target layout as electrically driven layout retargeting. The idea behind layout retargeting is that the default distribution of process variability band (PV-band) around nominal design edge is sub-optimal for electrical yield. The overall worst-case electrical yield can be improved by intentional shifting of the lithographic PV-band in the preferred direction. The PV-band can be shifted through retargeting the layout such that nominal target CD is biased up or down to obtain a desired shift. We present a linear programming formulation to calculate the optimal retargeting values for each device in the circuit. We apply the proposed retargeting flow to optimize electrical yield of an industrial SRAM design. Our results show that the electrically driven retargeting scheme improves the normalized SRAM yield from 0.89 (read access yield at outer lithographic contour) to 0.95 (read disturb yield at inner contour).

In this paper we present a modular approach which combines model based verification, pattern matching and machine learning methods in order to achieve a high accuracy over computing time ratio. We utilize pattern recognition technique using a supervised machine learning system (as opposed to pattern matching) to classify the patterns either as failures (hotspots) or non-failures, and we use pattern matching to detect all the outlier misses and false detections in each of the regions (based on the calibration set), which will be added or removed from the set of hotspots later on. Doing so allows us to do two things: Reduce the number of patterns that need to be pattern matched since only the outliers of the machine learning system need to be considered and more importantly it allows us to add trained predictability to new configurations that were not in the training set but that can be interpolated from the system. The results indicate that indeed it is possible to successfully combine Machine learning with pattern matching methods in order to achieve better predictability of errors of previously unseen data, while being exact in the treatment of previously observed data. We also explore possible avenues to further speed up the computation of the layout characterization process by inserting a global density grid, and assess the impact of model quality and aliasing under real detection conditions.

In this paper, we present an innovative approach to reduce power and accelerate timing closure by using simulated silicon-calibrated contours to predict the litho effects on transistor gates and perform litho-aware critical paths analysis. This approach is used to filter the false hold time violations and focus designers' actions on the most relevant violations. After silicon validation, the application of this technique to hold time fixing on a 90nm micro-controller unit product reduces the power increase and runtime of the hold buffer insertion. This study not only demonstrates the feasibility of the Litho-aware STA flow but also shows its value to reduce hold time fixing effort and power dissipation caused by buffer insertion.

For increasingly small and dense designs requiring adequate DOF, MEEF, and EL, numerous technologies have been employed to increase yield. Some techniques such as process optimization (i.e. SMO) are effective, but can be costly and time consuming, and are not easily modifiable once an initial choice is made. Design optimization can be done separately from knowledge of the fab's OPC correction, but for sub 32nm nodes the complexity and interaction of the design target shapes is becoming too complicated for predefined design rules to produce an acceptable result. In this paper we introduce a method called Lithographically Enhanced Edge Design (LEED) suited for IDMs. This joint target and mask optimization method takes into account the full OPC correction and process, and modifies the user's design in a controlled way so as to produce a new design with improved lithographic performance which can be used in place of the initial design. Control is given to the user so that inter-layer dependencies are not broken. Also, integrated target, mask, and source optimization is available in cases where target and mask optimization in not sufficient to produce adequate results. The use of ILT allows efficient target, mask, and source correction without extensive user OPC scripting and target modification sweeping. We show LEED results which enable production at 20x node.

Pitch-splitting type of double-patterning lithography is a necessity for critical layers for sub-22 nm technologies. Double patterning lithography techniques require additional masks to manufacture a single device layer. Consequently, double-patterning lithography brings overlay as a challenge that introduces additional variability to gate-to-contact coupling capacitances, device lengths, and contact resistances. These additional variability sources may negatively impact circuit performance. In this work, we provide analysis of digital and analog circuit blocks designed in 20 nm. We demonstrate the impact due to overlay-impacted change in resistance of self-aligned contacts. Furthermore, we provide layout optimization guidelines to reduce the impact of overlay. We demonstrate our methodology using TCAD and circuit simulations. We show that overlay impact may not be negligible, and pessimism reduction techniques should utilize suggested analysis and optimization methods.

BACKGROUND: Resist models for full-chip lithography simulation demand a difficult compromise between predictive accuracy and numerical speed. METHODS: Using a Gaussian approximation to the shape of the image-in-resist in the region of development near a feature edge, the integral normally solved numerically in the Lumped Parameter Model (LPM) can be evaluated analytically. As a result, a well known three-dimensional resist model (the LPM) can be used in only two-dimensions (the Gaussian LPM), greatly improving speed without significant loss of accuracy. RESULTS: For a positive resist, the image in the region of soluble resist material can be well approximated by a Gaussian image for all the mask features investigated. CONCLUSIONS: The Gaussian LPM is expected to have accuracy similar to the LPM but with substantially greater speed.

For process development of deep-subwavelength technologies, it has become accepted practice to use model-based simulation to predict systematic and parametric failures. Increasingly, these techniques are being used by designers to ensure layout manufacturability, as an alternative to, or complement to, restrictive design rules. The benefit of model-based simulation tools in the design environment is that manufacturability problems are addressed in a design-aware way by making appropriate trade-offs, e.g., between overall chip density and manufacturing cost and yield. The paper shows how library elements and the full ASIC design flow benefit from eliminating hot spots and improving design robustness early in the design cycle. It demonstrates a path to yield optimization and first time right designs implemented in leading edge technologies. The approach described herein identifies those areas in the design that could benefit from being fixed early, leading to design updates and avoiding later design churn by careful selection of design sensitivities. This paper shows how to achieve this goal by using simulation tools incorporating various models from sparse to rigorously physical, pattern detection and pattern matching, checking and validating failure thresholds.

Double patterning technology (DPT) is the only solution to enable the scaling for advanced technology nodes before EUV or any other advanced patterning techniques become available. In general, there are two major double patterning techniques: one is Litho-Etch-Litho-Etch (LELE), and the other is sidewall spacer technology, a Self-Aligned Double Patterning technique (SADP). While numerous papers have previously demonstrated these techniques on wafer process capabilities and processing costs, more study needs to be done in the context of standard cell design flow to enable their applications in mass production. In this paper, we will present the impact of DPT on logic designs, and give a thorough discussion on how to make DPT-compliant constructs, placement and routing using examples with Cadence's Encounter Digital Implementation System (EDI System).

The paper describes a process/design co-optimization effort based on an SRAM design to enable a single exposure contact process for the 28nm technology half node. As a start, a change to the wiring concept of the standard SRAM design was implemented. The resulting individual contact layer elements may seem even more resolution critical to the casual observer. But in reality, the flexibility for source-mask optimization had been significantly improved. In a second step, wafer targets and mask dimension options (using various kinds of OPC methods and SRAF strategies) were run through several optimization iterations. This included interlevel considerations due to stringent overlap requirements. Several promising SRAM design as well as mask options were identified and experimentally verified to finally converge to an optimum mask and wafer target layout. Said optimum solution still supports an automated OPC approach using standard EDA tools and off the shelf OPC strategies. In a last step, a 1Mbit electrically testable SRAM was designed and manufactured together with alternative SRAM designs and process options. After explaining the changes to the wiring of the SRAM design, the paper discusses in great detail various mask optimization solutions and their consequences on wafer target and printability. Simulation and experimental results are compared and the concluding optimized solution is explained. Furthermore, some key lithography and etch process elements that became the single exposure process enabler are explained in more detail. Finally, the paper will take a look at electrical results of the 1Mbit electrically testable SRAM as the ultimate proof of concept.

Conventional resolution enhancement techniques (RET) are becoming increasingly inadequate at addressing the challenges of subwavelength lithography. In particular, features show high sensitivity to process variation in low-k1 lithography. Process variation aware RETs such as process-window OPC are becoming increasingly important to guarantee high lithographic yield, but such techniques suffer from high runtime impact. An alternative to PWOPC is to perform retargeting, which is a rule-assisted modification of target layout shapes to improve their process window. However, rule-based retargeting is not a scalable technique since rules cannot cover the entire search space of two-dimensional shape configurations, especially with technology scaling. In this paper, we propose to integrate the processes of retargeting and optical proximity correction (OPC). We utilize the normalized image log slope (NILS) metric, which is available at no extra computational cost during OPC. We use NILS to guide dynamic target modification between iterations of OPC. We utilize the NILS tagging capabilities of Calibre TCL scripting to identify fragments with low NILS. We then perform NILS binning to assign different magnitude of retargeting to different NILS bins. NILS is determined both for width, to identify regions of pinching, and space, to locate regions of potential bridging. We develop an integrated flow for 1x metal lines (M1) which exhibits lesser lithographic hotspots compared to a flow with just OPC and no retargeting. We also observe cases where hotspots that existed in the rule-based retargeting flow are fixed using our methodology. We finally also demonstrate that such a retargeting methodology does not significantly alter design properties by electrically simulating a latch layout before and after retargeting. We observe less than 1% impact on latch Clk-Q and D-Q delays post-retargeting, which makes this methodology an attractive one for use in improving shape process windows without perturbing designed values.

Continuous shrinkage of design rule (DR) in ultra-large-scale integrated circuit (ULSI) devices brings about greater difficulty in the manufacturing process. The keys to meeting small process margin are adequate extraction of critical dimension (CD) tolerance for each object and budgeting the tolerance for each process step. Furthermore, to extract adequate tolerance, design intent in terms of electrical behavior should be carefully considered. Electrical behavior is carefully verified in design stages using various electronic design automation (EDA) tools. However, once the design data is converted to layout data and signed off, most of the design intent is abandoned and unrecognized in the process stage. Thus, instead of essential tolerance assignment according to layout-related design intent, uniform and redundant tolerance is used, and so excess tolerance is assigned for some layouts. To solve the problem described above, a tolerance-based manufacturing system utilizing flexible layout-dependent speculation derived from design intent has been discussed. In this paper, test flow utilizing design intent is developed. In the flow, electrical small-margin spots are extracted, verified with customized criteria according to the tolerance derived from design intent, and fixed in the process. The proposed flow is examined and validated for the application to 40nm node test chip.

As the optical lithography advances into the sub-30nm technology node, many candidates of the lithography have been discussed. Double pattering technology (DPT) has been a primary lithography candidate for the direct contact of the sub-30nm device due to a merit of a low mask cost and process stability compared to the extreme ultraviolet lithography (EUV). However, the major concerns of DPT are the critical dimension (CD) skew and overlay error between the 1st and 2nd pattering, which cause the degradation of electrical performance such as the mismatch of the pair transistors of the analog circuit. If we assume there is the 10nm position difference of the direct contact between the pair transistors, which is induced by the overlay error between the 1st and 2nd pattering of the DPT process, then the threshold voltage difference between the pair transistors is about 10%. Therefore, the direct contact of the pair transistors must be decomposed as the same color to minimize the threshold voltage variation of the analog circuit. Since the DPT process of the direct contact is the litho-etch-litho-etch (LELE) process, there are the CD variations induced by the global density difference between the 1st and 2nd mask. In this paper, we newly develop the DPT methodology to decompose the direct contact of the pair transistors to the same mask using the optimized marking polygons, decomposition algorithm. In addition, the decomposition algorithm for the density balancing between the 1st and 2nd mask is developed to minimize the CD variations caused by the density difference. Our main contributions are as follows. (1) The optimal marking polygons, which group the direct contacts of the pair transistors, are designed to consider the layout configurations of pair transistors. The space between each contact located on the same marking polygon is designed to be larger than the resolution limit of the single exposure, so that the contacts grouped by the same marking polygon can be decomposed as the same color. (2) The whole contacts grouped by the same marking polygon are changed to the representative single contact, and then the colors of the grouped contacts are assigned by the representative single contact and its surrounded contacts. (3) After decomposing the layout to consider the contact on the pair transistors, the remaining contacts, which is not necessary to decompose from the view point of the patterning limit, are decomposed to satisfy the density balance between the 1st and 2nd mask. Consequently, we can achieve the pattering margin and electrical performance of sub-30nm device by applying the new DPT methodology to the direct contact.

The traditional design rule paradigm of defining the illegal areas of the design space has been deteriorating at the advanced technology nodes. Radical design space restrictions, advocated by the regular design fabrics methodology, provide an opportunity to reshape the design/manufacturing interface by constraining the layout to a set of allowable patterns. As such, this would allow for guaranteed convergence of the source mask optimization techniques (SMO) and complete validation of the legal design space during technology development and ramp. However, the number of the unique patterns generated by the layout adhering to even the simplistic gridded design rules prohibits this approach. Nevertheless, we have found that just 10% of the unique geometric patterns are sufficient to represent 90% of all layout pattern instances. Furthermore, the overall number of layout patterns on Active, Contact, and Metal-1 design layers can be reduced through modification of existing layout shapes in the final layout database and insertion of non-essential layout features. Unlike the 'dummy fill' used for chemical mechanical polishing (CMP), the newly added shapes must resemble the patterning of the functional design features and be inserted in close proximity to them. In this paper, we evaluate the digital circuit performance impact of the additional layout parasitics introduced by these 'dummy' features. In particular, we have found that a significant pattern count reduction can be achieved with minimal performance penalty. These results have been used at PDF Solutions to enable a correct by construction layout style, such as the templates and connectors-based layout methodology presented in the companion paper.

Maintaining the microelectronics industry's aggressive pace of density scaling beyond the resolution limits of optical lithography is forcing the introduction of double-patterning technology (DPT) that effectively doubles the pattern density achievable with 193nm optical lithography. This paper investigates the degree to which DPT affects design tools, layout methodologies, and data standards. Design solutions are demonstrated and the efficiency of various double-patterning aware design methodologies is compared based on the first metal level of a 20nm-node standard cell design flow. Necessary design-tool and data-standard requirements for a DPT-aware standard cell design flows are enumerated and summarized.

Self-aligned double pattering (SADP) has been adapted as a promising solution for sub-30nm technology nodes due to its lower overlay problem and better process tolerance. SADP is in production use for 1D dense patterns with good pitch control such as NAND Flash memory applications, but it is still challenging to apply SADP to 2D random logic patterns. The favored type of SADP for complex logic interconnects is a two mask approach using a core mask and a trim mask. In this paper, we first describe layout decomposition methods of spacer-type double patterning lithography, then report a type of SADP compliant layouts, and finally report SADP applications on Samsung 22nm SRAM layout. For SADP decomposition, we propose several SADP-aware layout coloring algorithms and a method of generating lithography-friendly core mask patterns. Experimental results on 22nm node designs show that our proposed layout decomposition for SADP effectively decomposes any given layouts.

In today's semiconductor industry, prior to wafer fabrication, it has become a desirable practice to scan layout designs for lithography-induced defects using advanced process window simulations in conjunction with corresponding manufacturing checks. This methodology has been proven to provide the highest level of accuracy when correlating systematic defects found on the wafer with those identified through simulation. To date, when directly applying this methodology at the full chip level, there has been unfavorable expenses incurred that are associated with simulation which are currently overshadowing its primary benefit of accuracy - namely, long runtimes and the requirement for an abundance of cpus. Considering the aforementioned, the industry has begun to lean towards a more practical application for hotspot identification that revolves around topological pattern recognition in an attempt to sidestep the simulation runtime. This solution can be much less costly when weighing against the negative runtime overhead of simulation. The apparent benefits of pattern matching are, however, counterbalanced with a fundamental concern regarding detection accuracy; topological pattern identification can only detect polygonal configurations, or some derivative of a configuration, which have been previously identified. It is evident that both systems have their strengths and their weaknesses, and that one system's strength is the other's weakness, and vice-versa. A novel hotspot detection methodology that utilizes pattern matching combined with lithographic simulation will be introduced. This system will attempt to minimize the negative aspects of both pattern matching and simulation. The proposed methodology has a high potential to decrease the amount of processing time spent during simulation, to relax the high cpu count requirement, and to maximize pattern matching accuracy by incorporating a multi-staged pattern matching flow prior to performing simulation on a reduced data set. Also brought forth will be an original methodology for constructing the core pattern set, or candidate hotspot library, in conjunction with establishing hotspot and coldspot pattern libraries. Lastly, it will be conveyed how this system can automatically improve its potential as more designs are passed through it.

The mask requirements for 110nm half-node BiCMOS process were analyzed with the goal to meet customer needs at lower cost and shorter cycle times. The key differentiating features for this technology were high density CMOS libraries along with high-power Bipolar, LDMOS and DECMOS components. The high voltage components were characterized by transistors that formed cylindrical junctions. The presence of curved features in the data is particularly detrimental to the write time on a 50KeV vector mask writer. The mask write times have a direct impact on both mask cost and cycle time. Design rules also permit rectangular or stretched contacts to allow conductance of high currents. To meet customer needs but still manage the computational lithography overhead as well as the patterning process performance, this process was evaluated in terms of computational lithography and photomask co-optimization for the base-line 50KeV vector and laser mask-writers. Due to the differences in imaging and processing of the different mask writing systems, comparative analysis of critical dimension (CD) performance both in terms of linearity and pitch was done. Differences in imaging on silicon due to mask fidelity were also expected and characterized. The required changes in OPC necessary to switch to the new mask process were analyzed.

Amongst the possible double patterning strategies for sub 32nm processes, self-aligned double patterning (SADP) has moved from Flash-only processes to more general purpose devices. The reason is that while litho-etch- litho-etc (LELE) process was originally preferred due to its simplicity and relative low cost, its sensitivity to overlay error has prompted the search for other methods. Although the basic SADP process is fairly robust against the overlay error, the robustness of 2D SADP method strongly depends on layout and decomposition styles and decomposability compliance. In this paper, we first discuss different printability challenges for SADP method. Afterward, we propose a SADP-aware detailed routing method, by applying a correct-by-construction approach, to provide SADP-friendly layouts. This method performs detailed routing and layout decomposition concurrently to prevent litho-limited layout configurations. Experimental results show that, compared with a SADP-blind detailed router, the proposed method achieves considerable robustness against lithography imperfection in expense of tolerable wire length overhead.

We propose a partial least squares (PLS)-preconditioned importance sampling method for yield estimation. The method makes use of the rotating vector obtained through PLS regression, and finds the boundary point along the vector by line search. A biased distribution is constructed around that point for subsequent importance sampling simulation. This method is shown to be much more stable and efficient than existing approaches and is validated via an SRAM example.

Semiconductor industry has been experiencing rapid and continuous shrinkage of feature size along with Moore's law. As the VLSI technology scales down to sub 40nm process node. Control of critical dimension (CD) and Extraction of Unanticipated weak point pattern effects known as "hot spots" becoming more challenging and difficult. Therefore, experimental full-chip inspection methodologies for Control of critical dimension (CD) and hotspots extraction are necessary in order to reduce Turn-Around-Time (TAT) for steep ramp up Manufacture. In this paper, we introduce the concepts of an innovative reduction Turn-around-time (TAT) in manufacture production with applications of DBV (Design Based Verification). The noble methodologies employed by our own technology with application of DBV are highly advantageous for exactly determining for process judgment go or no-go about wafer process in mass-production of memory device.

In contrast to defect limited yield loss, systematic yield detractors like lithography hotspots may cause a huge yield loss per event. For 45 nm and subsequent technology nodes, those findings are for this reason classified as DRC-like errors and need to be fixed before tape-out. In this paper, we report a comparison - from the use-model point-of-view - of two different methods for removal of lithography hotspots. First, a rip-up & re-routing and second, a guided-repair approach will be presented. This includes a discussion of the impact in the routing context, mainly radius of influence and timing closure, aspects of multiple layer involvement and the layout hierarchy, and the limitations caused by the layout grid.

This paper presents a model-based Chemical Mechanical Polishing (CMP) Design for Manufacturability (DFM) () methodology that includes an accurate prediction of post-CMP copper interconnect topographies at the advanced process technology nodes. Using procedures of extensive model calibration and validation, the CMP process model accurately predicts post-CMP dimensions, such as erosion, dishing, and copper thickness with excellent correlation to silicon measurements. This methodology provides an efficient DFM flow to detect and fix physical manufacturing hotspots related to copper pooling and Depth of Focus (DOF) failures at both block- and full chip level designs. Moreover, the predicted thickness output is used in the CMP-aware RC extraction and Timing analysis flows for better understanding of performance yield and timing impact. In addition, the CMP model can be applied to the verification of model-based dummy fill flows.

In IC manufacturing, the performance of standard cells often varies due to process non-idealities. Some research work on 2-D cell characterization shows that the timing variations can be characterized by the timing model. However, as regular design rules become necessary in sub-45nm node circuit design, 1-D design has shown its advantages and has drawn intensive research interest. The circuit performance of a 1-D standard cell can be more accurately predicted than that of a 2-D standard cell as it is insensitive to layout context. This paper presents a characterization methodology to predict the delay and power performance of 1-D standard cells. We perform lithography simulation on the poly gate array generated by dense line printing technology, which constructs the poly gates of inverters, and do statistical analysis on the data simulated within the process window. After that, circuit simulation is performed on the printed cell to obtain its delay and power performance, and the delay and power distribution curves are generated, which accurately predict the circuit performance of standard cells. In the end, the benefits of our cell characterization method are analyzed from both design and manufacturing perspectives, which shows great advantages in accurate circuit analysis and yield improving.

Early lithographic hotspot detection has become increasingly important in achieving lithography-friendly designs and manufacturability closure. Fast physical verification tools employing pattern matching or machine learning techniques have emerged as great options for detecting hotspots in the early design stages. In this work, we propose a characterization methodology that provides measurable quantification of a given hotspot detection tool's capability to capture a previously seen or unseen hotspot pattern. Using this methodology, we conduct a side-by-side comparison of two hotspot detection methods-one using pattern matching and the other based on machine learning. The experimental results reveal that machine learning classifiers are capable of predicting unseen samples but may mispredict some of its training samples. On the other hand, pattern matching-based tools exhibit poorer predictive capability but guarantee full and fast detection on all their training samples. Based on these observations, we propose a hybrid detection solution that utilizes both pattern matching and machine learning techniques. Experimental results show that the hybrid solution combines the strengths of both algorithms and delivers improved detection accuracy while sacrificing little runtime efficiency.

This paper presents an approach for compressing litho hotspot pattern library that complies with general purpose pattern matching engine (GPPME). This approach incorporates two techniques to achieve optimal pattern reduction. The first technique excludes polygons outside the optical diameter to reduce numerical noise related to a square ambit which artificially may affect a hotspot location. The second technique determines the common geometrical structures between patterns and inserts adaptive edge tolerance constraints for each individual pattern. The performance of the resulting compressed patterns is then compared to that of running the complete library of exact matches using an optimized exact pattern matching engine (OEPME). The results indicate that compression rates giving number of compressed patterns in the order of hundreds can achieve better performance than running an optimized exact pattern matcher for the whole library while maintaining the original quality of results.

Traditionally model based CMP check and hotspot detection are only done at the top level of the design because full chip assembly is required to capture CMP long range effect. When manufacturing hotspots are found just before tape out and layout modification is required, this can disrupt the overall schedule by repeating the verification steps with the changed layout. Hence getting feedback at early design stage is critical to ensure that the design is correct by construction. In this paper, we present a model-based CMP-DFM methodology which is used at early design phases to avoid CMP related manufacturing failures. An accurate CMP model has been developed and used to predict surface topographies for 32nm designs as well as physical hotspots caused by dishing, erosion, and depth of focus. We demonstrate how to apply a characterized 32nm CMP physical model to run block level simulation with little or no context information. The block level simulation methodology allows designers to check block robustness against any possible surrounding environments in which the block may be placed. This approach can be taken for corner case analysis in CMP-aware RC extraction.

Below 40nm design node, systematic variation due to lithography must be taken into consideration during the early stage of design. So far, litho-aware design using lithography simulation models has been widely applied to assure that designs are printed on silicon without any error. However, the lithography simulation approach is very time consuming, and under time-to-market pressure, repetitive redesign by this approach may result in the missing of the market window. This paper proposes a fast hotspot detection support method by flexible and intelligent vision system image pattern recognition based on Higher-Order Local Autocorrelation. Our method learns the geometrical properties of the given design data without any defects as normal patterns, and automatically detects the design patterns with hotspots from the test data as abnormal patterns. The Higher-Order Local Autocorrelation method can extract features from the graphic image of design pattern, and computational cost of the extraction is constant regardless of the number of design pattern polygons. This approach can reduce turnaround time (TAT) dramatically only on 1CPU, compared with the conventional simulation-based approach, and by distributed processing, this has proven to deliver linear scalability with each additional CPU.

This paper presents an effective methodology for etch PPC (Process Proximity Correction) of 20 nm node DRAM (Dynamic Random Access Memory) gate transistor. As devices shrinks, OCV(On chip CD Variation) control become more important to meet the performance goal for high speed in DRAM. The main factors which influence OCV are mask, photo, etch PPE (Process proximity effect) in DRAM gate. Model based etch PPC is required to properly correct Etch PPE as device density increases. To improve OCV in DRAM gate, we applied new type of etch loading kernel. It is called Vkernel which accounts for directional weight from the point of interest. And we optimized the etch PPC convergence by optimizing the etch PPC iteration. Because of density difference between spider mask and real gate mask, the skew difference occurs between them. We tested the effect of long range density using same real gate pattern clip by varying mask open image size from 0.5 ~ 10 mm. The ADI CD difference was on average in the order on 2 nm for varying mask open image size. But the ACI CD difference (the average of CD range by varying open image size) was very noticeable (about 15 nm). This result shows that etch skew affected by long range density by mm unit size. Due to asymmetrical pattern in real gate mask, spider mask which have symmetrical patterns is necessarily used to make PPC model. The etch skew of real pattern clip in spider mask was not also the same for the real pattern in real gate mask. To reduce this skew difference between spider mask and real mask, we applied open field mask correction term and long range density effects correlation equation to PPC modeling. There was noticeable improvement in the accuracy of PPC model. By applying these improvement items, OCV of 20 nm node DRAM gate is shown to improve up to 67%.

Fabricating defect-free mask blanks remains a major "show-stopper" for adoption of EUV lithography. One promising approach to alleviate this problem is reticle floorplanning with the goal of minimizing the design impact of buried defects. In this work, we propose a simulated annealing based gridded floorplanner for single project reticles that minimizes the design impact of buried defects. Our results show a substantial improvement in mask yield with this approach. For a 40-defect mask, our approach can improve mask yield from 53% to 94%. If additional design information is available, it can be exploited for more accurate yield computation and further improvement in mask yield, up to 99% for a 40-defect mask. These improvements are achieved with a limited area overhead of 0.03% on the exposure field. Defect-aware floorplanning also reduces sensitivity of mask yield to defect dimensions.

A fully automated system for process variability analysis of high density standard cell was developed. The system consists of layout analysis with device mapping: device type, location, configuration and more. The mapping step was created by a simple DRC run-set. This database was then used as an input for choosing locations for SEM images and for specific layout parameter extraction, used by SPICE simulation. This method was used to analyze large arrays of standard cell blocks, manufactured using Tower TS013LV (Low Voltage for high-speed applications) Platforms. Variability of different physical parameters like and like Lgate, Line-width-roughness and more as well as of electrical parameters like drive current (Ion), off current (Ioff) were calculated and statistically analyzed, in order to understand the variability root cause. Comparison between transistors having the same W/L but with different layout configurations and different layout environments (around the transistor) was made in terms of performances as well as process variability. We successfully defined "robust" and "less-robust" transistors configurations, and updated guidelines for Design-for-Manufacturing (DfM).

In this work, we present a new technique to detect non-Litho-Friendly design areas based on their Aerial Image signature. The aerial image is calculated for the litho target (pre-OPC). This is followed by the fixing (retargeting) the design to achieve a litho friendly OPC target. This technique is applied and tested on 28 nm metal layer and shows a big improvement in the process window performance. For an optimized Aerial-Image-Retargeting (AIR) recipe is very computationally efficient and its runtime doesn't consume more than 1% of the OPC flow runtime.

We identify most recent sources of transistor layout dependent effects (LDE) such as stress, lithography, and well proximity effects (WPE), and outline modeling and analysis methods for 28 nm. These methods apply to custom layout, standard cell designs, and context-aware post-route analysis. We show how IC design teams can use a model-based approach to quantify and analyze variability induced by LDE. We reduce the need for guard-bands that negate the performance advantages that stress brings to advanced process technologies.

Double-patterning technology (DPT) has been a primary lithography candidate of the sub-30nm technology node. The major concern of DPT is the critical dimension (CD) skew and overlay error between 1st and 2nd patterning, which cause the degradation of the electrical performance in terms of timing delay. In this paper, we newly develop a systematic method to determine the DPT scheme and the proper process specification using a statistical approach in perspective of the pattering and electrical performance. Applying the method to the bit-line layer of the sub-30nm DRAM device, we determine the DPT scheme (i.e. either litho-etch-litho-etch (LELE) or self-aligned double pattering (SADP) to avoid the patterning hotspots. In addition, analyzing the statistical simulation result, we provide the process specification and exposing sequence of two masks to avoid the electrical degradation.