An optimal control scheme is designed to improve repeatability by minimizing the loading effects induced by the common processing condition of placement of a semiconductor wafer/photomask at ambient temperature on a large thermal-mass bake plate at processing temperature. The optimal control strategy is a model-based method using linear programming to minimize the worst-case deviation from a nominal temperature set-point during the load disturbance condition. This results in a predictive controller that performs a pre-determined heating sequence prior to the arrival of the wafer as part of the resulting feedforward/feedback strategy to eliminate the load disturbance. This procedure is based on an empirical model generated from data obtained during closed-loop operation. It is easy to design and implement for conventional thermal processing equipment. Experimental results are performed for a commercial conventional bake plate and depict an order-of-magnitude improvement in the settling time and the integral-square temperature error between the optimal predictive controller and a feedback controller for a typical load disturbance.

Oxide chemical mechanical polishing process control has been limited in the past to off-line verification of layer thicknesses. This procedure causes a significant delay in feedback due to the off-line scrubbing process and wafer transfer. Recently, systems have been introduced to endpoint on the polish platen itself using interference-based methods. While these approaches allow a better control of the thickness remaining, they do not replace the off-line measurement because the correlation of the signal with the absolute thickness is difficult and no uniformity information is retrieved. An integrated measurement tool, that provides feedback immediately after the polish cycle, represents an intermediate solution. This methodology reduces the set-up time significantly and allows a 100% control of the outgoing product with increased throughput versus using an off-line measurement system. In respect to optimizing the wafer to wafer variation within lot, the polish time can be adjusted for the subsequent wafer based on the previously polished wafers. The utilized closed loop control algorithm (PID-type) can take the incoming distribution into account as well as first wafers effects and changes in layer type. Considering the results of the measurement of previously polished wafers, the polish time for the following wafer is adjusted to center the thickness distribution around the target. A system as described was implemented on an IPEC 472 polisher at Motorola MOS6. Lot charts showing thickness variations before and after the implementation of CLC have been recorded showing an improved distribution with CLC feedback leading to improvements in process capability by a factor of 1.5. In summary, integrated metrology with closed loop control provides improved process control as well as enhanced throughput for oxide CMP.

The effect of varying time and temperature profile at the PEB step on a 250 nm isolated line is studied for an Acetal and an ESCAP type Deep UV (DUV) resist. Experimental studies on the Acetal resist resulted in very non-linear Critical Dimension (CD) sensitivities with CD variation largest for low Post Expose Bake (PEB) temperature and short PEB time. A global CD model was created by fitting experimental data to a first order kinetics equation. An effective activation energy of 50 Kcal/mole was obtained for the Acetal resist whereas PROLITH simulations for an ESCAP type resist gave 69 Kcal/mole. These results are consistent with the well-documented diffusion- controlled deprotection reaction taking place during the PEB process. The global CD model was then used to investigate the impact of transient and steady-state temperature profiles on CD control. In order to achieve this goal, actual 2 dimensional wafer temperature profiles were input to the global CD model and PEB-induced CD variation was calculated during each sampling period of the 17 temperature readings across the wafer as a function of time. The resultant time- evolution of the PEB-induced CD variation was used to infer the relative importance of the transient and steady-state component of temperature profiles. At the low PEB temperature of 90 degrees Celsius for the Acetal resist, transient effects dominate for a nominal 90 second process. Slower deprotection reaction yields large CD's at 356 nm and predicted PEB-induced CD variation of 6.9 nm. At 100 degrees Celsius, transient effects are less prevalent but still present. Tight steady- state and transient temperature uniformity along with wafer- wafer temperature profile repeatability and stringent control of process timing and delays are important. At 110 degrees Celsius, transient effects are dominant early in the process and they are completed within about 50 seconds in this model. However as photoacid is lost to competing reactions and the time necessary for deprotection is extended, even in this case transients could still play a part in final CD results. In general, both mean CD and CD variation results improve with increasing PEB temperature for a 90 second PEB time. PROLITH simulations using ESCAP resist parameters and actual measured CD profiles both support these model predictions. Improved resist formulations along with advanced photoresist processing tool layout, wafer-handler scheduler and PEB module designs are all necessary ingredients for minimum PEB-induced CD variation.

This paper discusses the integration and development of advanced process control technologies with AMD's Fab25 factory systems using the Advance Process Control Framework. The Framework is an open software architecture that allows the integration of existing factory systems, such as the manufacturing execution systems, configurable equipment interfaces, recipe management systems, metrology tools, process tools, and add-on sensors, into a system which provides advanced process control specific functionality. The Advanced Process Control Framework project was formulated to enable effective integration of Advanced Process Control applications into a semiconductor facility to improve manufacturing productivity and product yields. The main communication link between the factory system and the Framework is the Configurable Equipment Interface. It interfaces through a specialized component in the framework, the Machine Interface, which converts the factory system communication protocol, ISIS, to the Framework protocol, CORBA. The Framework is a distributed architecture that uses CORBA as a communication protocol between specialized components. A generalized example of how the Framework is integrated into the semiconductor facility is provided, as well as a description of the overall architecture used for process control strategy development. The main development language, Tcl/Tk, provides for increased development and deployment over traditional coding methods.

Formation of the MOS-FET polysilicon gate structure is a critical step in integrated circuit manufacturing. Control of poly-gate Critical Dimension (CD's) greatly affects revenue from microprocessor production. Poly-gate CD's correlate strongly to speed. As a result, variation in CD control causes unsaleable slow parts, high revenue fast parts, or scrapped high leakage product from overly fast parts. Controlling to the optimal value CD value, however, it is a difficult task due to the continual drift and step changes that occur in the photolithography and etch tools. As a result of this need, AMD's Fab 25 developed an automated run-to-run controller of poly-gate CD's as part of an Advanced Process Control (APC) initiative. From the perspective of both control and manufacturability, Fab 25's Run-to-Run controller of poly-gate Critical Dimension (CD) has been a critical enabler of our success in manufacturing the K6 product. This paper discusses the architecture, algorithm and results of the poly-gate CD control system.

Determining the required polish time in oxide chemical mechanical polishing (CMP) is more challenging than in metal CMP, where the metal is polished until a polish stop is reached. In oxide CMP, the objective is to remove topography caused by depositing an oxide layer over metal lines, stopping at a target thickness. It is important that this target thickness be maintained for subsequent process steps. Because of the device and layer dependence of oxide CMP and the drift in the flat film polish rate with time it is helpful to use a pilot polish time calculation algorithm which considers these effects. An algorithm of this type and its use with computer integrated manufacturing has been described. The implementation of this algorithm has produced a substantial decrease in the frequency of touch polishing pilot wafers and has essentially eliminated the need for second pilot wafers, and may eventually eliminate the need for flat film rate qualification. This system has proven beneficial in reducing manufacturing errors and has improved tool availability.

Preliminary performance data is presented for a new thermal processing module. The system is directed towards conducting the temperature sensitive baking and chilling steps for chemically amplified photoresists. The module is comprised of 49 individual heating zones. The zones can be controlled independently with separate temperature sensing, actuation and feedback control mechanisms. A supervisory control strategy is applied to coordinate the individual zones. An in-situ chill plate is used to enable a temperature controlled cool-down phase without the need for substrate movement. Results are presented to demonstrate temperature control over the plate to within plus or minus 0.02 degrees Celsius. Wafer temperature is controlled to within plus or minus 0.05 degrees Celsius as measured at 5 sites. Photomask processing results are presented depicting steady-state control to within plus or minus 0.05 degrees Celsius as measured at 16 sites within one quadrant of the substrate. The advantages of the system are discussed including better temperature uniformity than conventional systems and the ability to conduct multiple experiments in a single run by biasing the setpoint across the substrate.

This research examines the optimum spacing between the Physical Vapor Deposition (PVD) target and the wafer substrate, at various stages in the erosion life of the target. As the target erodes, the surface becomes uneven with ring shaped grooves. This effects the radial distribution of material flux onto the wafer, and requires the wafer to be moved further from the target. The optimal target to wafer spacing is plotted against target lifetime for different types of chamber configurations and target materials. Target materials are Ti, TiN, and Al, and chamber configurations are standard Magnetron PVD, Collimated PVD, and Ionized Metal Plasma (IMP) PVD. TiN chambers with Dura TTN magnets show predictable behavior during the life of the target, while Type A magnets and all other chamber configurations show almost now drift in the optimum spacing. Thus, it was decided only Dura TTN (TiN) chambers required spacing compensation. Rate-of- change constants for TiN chambers were input into software provided by Applied Materials, to dynamically adjust the spacing as the target erodes. Thickness uniformity of less than 1% was maintained throughout the target's 1600 KWHrs life.

The planarization and recessing of polysilicon to form a plug are processes of increasing importance in silicon IC fabrication. While this technology has been developed and applied to DRAM technology using Trench Storage Capacitors, the need for such processes in other IC applications (i.e. polysilicon studs) has increased. Both planarization and recess processes usually have stringent requirements on etch rate, recess uniformity, and selectivity to underlying films. Additionally, both processes generally must be isotropic, yet must not expand any seams that might be present in the polysilicon fill. These processes should also be insensitive to changes in exposed silicon area (pattern factor) on the wafer. A SF₆ plasma process in a polysilicon DPS (Decoupled Plasma Source) reactor has demonstrated the capability of achieving the above process requirements for both planarization and recess etch. The SF₆ process in the decoupled plasma source reactor exhibited less sensitivity to pattern factor than in other types of reactors. Control of these planarization and recess processes requires two endpoint systems to work sequentially in the same recipe: one for monitoring the endpoint when blanket polysilicon (100% Si loading) is being planarized and one for monitoring the recess depth while the plug is being recessed (less than 10% Si loading). The planarization process employs an optical emission endpoint system (OES). An interferometric endpoint system (IEP), capable of monitoring lateral interference, is used for determining the recess depth. The ability of using either or both systems is required to make these plug processes manufacturable. Measuring the recess depth resulting from the recess process can be difficult, costly and time- consuming. An Atomic Force Microscope (AFM) can greatly alleviate these problems and can serve as a critical tool in the development of recess processes.

Metal deposition equipment typically sputter more from the center of the target than the edge. Features on the wafer can cause a shadowing effect where the metal accumulates on the surfaces that are more incident. This will result in an apparent image shift if viewed from the top. The misplacement will be minimized near the center of the wafer and will be worse toward the edge. Since the actual position of the alignment mark is not visible, only the misplaced image as viewed from the metal covering the mark, direct inline alignment measurement is not possible with optical or SEM methods. Cross sections show that the misplacement is linear and symmetric about the wafer center and takes the form of a scaling misalignment. When overlay is measured on a wafer using traditional means, the scaling correction is added mathematically to the data to compensate for the inability of the tool to measure the actual alignment. Using this technique, standard overlay tools can be used to measure alignment on opaque films.

Ceramic susceptors were retrofitted into the 200 mm Plasma Enhanced Chemical Vapor Deposition (PECVD) Dielectric toolsets to increase the Mean Time Before Failure (MTBF) caused by warping of the original Aluminum susceptors. Although the hardware retrofit resulted in a more stable deposition process, the within wafer uniformity remained consistently high. Designed experiments were performed and determined that the new Ceramic susceptors exhibited a uniformity signature that enabled the process to be optimized using electrode spacing. This process change resulted in a 20% uniformity improvement on both control and product wafers without adversely affecting Yield and IV parameters. Effects of the change on various other deposition parameters were also studied and determined to be minimal. After committee review, this process change was implemented on all PECVD Dielectric 1 toolsets and has been stable over time.

In this paper, we describe the application of the edge width measurement to the monitoring of contact hole openings in an attempt to evaluate its ultimate limitations due to tool resolution, measurement algorithm, and process sensitivity. Substantial variations in the top-down SEM image and waveform translated to smaller but still detectable variations in measured edge width using a max slope/linear regression algorithm. The images and waveforms indicate the top-down SEM resolution to be sufficient to detect process variations, but the measured results suggest optimization of the algorithms for this specific purpose will be necessary.

We demonstrate the measurement capabilities of the newly developed Atomic Force Profiler (AFP) as a CMP process metrology tool. AFP combines a TappingMode atomic force microscopy (AFM) with a long scan profiler stage and can be used to characterize post-CMP local and global planarization for current and future generations of device manufacturing. The AFP enables CMP measurements of dishing, erosion, plug recess, and surface texture, providing adequate lateral resolution to image individual deep sub-micron device features as well as capability to profile long scans across multiple dies. In this paper we demonstrate that AFP can be used for the process development and production monitoring of metal CMP. Automated measurement of deep sub-micron W plug recess/protrusion, damascene Cu lines recess/protrusion, as well as erosion due to W or Cu structures is presented.

For some time, various techniques have been available for detecting the endpoint of chemical mechanical polish (CMP) processes for the removal of metal or dielectric layer thickness. Commercially available systems employ techniques based on motor current, infrared (IR), and various interferometer-based methods. Attempts were made to implement several such commercial systems and they failed for a variety of reasons, ranging from unreliable hardware components to inadequate signal processing features. To provide a reliable, high-performance endpoint detection system, a new endpoint system was developed for a SpeedFam Auriga polisher. Two additional requirements were added in that the resulting system should need essentially no operator intervention and should be able to detect endpoints for any of the several metal polishing processes. The system developed for this project included data monitoring and control capabilities with digital signal processing, algorithm selection for endpoint detection, and fault detection. The carrier speed controller output signal (DAC) was processed through a digital filter to provide smooth curves that had a characteristic suitable for endpoint detection and fault detection. Any disturbances and noise not removed by the digital filtering would have to be accounted for in the endpoint algorithm and avoided as a possible source of detection confusion. Characteristics of the filtered DAC curves varied depending on the layers being polished and the consumables used (including slurries). The SpeedFam tools for which the endpoint system was developed were capable of polishing several wafers simultaneously. Thus it was necessary that the new system would detect either a batch endpoint for all wafers being polished, or control the downforce on individual carriers. The new system was designed to use the output of a carrier speed controller or an JR signal to detect endpoints, depending on the specific process. It was also possible to analyze the filtered carrier DAC signals for indications of faults related to carrier spindle condition and slurry quality. Temperature variations of the polishing pad were measured with an JR detector and found to indicate progress of the polishing process. When a single JR detector was used for measurement of a spot on a rotating pad for a tool with multiple carriers, the detected thermal signal indicated the average polishing progress for all wafers. This project illustrates the use of digital filter analysis to isolate key process characteristics in measurement signals while rejecting signal noise and process variations due to consumable and wafer properties.

Today's advanced IC manufacturers are already beginning production on 0.18 micrometer process technology. This requires gate oxidation processes that are capable of thicknesses in the 30 angstrom to 40 angstrom range. The gate oxide thickness specification will be pushed even lower as the industry moves toward sub-0.18 micrometer technology in the next few years. In order to maintain device performance and yields, it is necessary that the gate oxide thickness be very tightly controlled. Current ellipsometry techniques do not provide the precision-to-tolerance ratios required for good statistical process control of these ultra-thin gate oxides. This work demonstrates that a significant portion of the error in ellipsometry measurements is the result of organic surface contamination. Furthermore, the Rapid Optical Surface Treatment is shown as a good method for removing organic surface contaminants and extending the capabilities of ellipsometry techniques for ultra-thin gate oxides.

While integrated circuit manufacturing has demonstrated continuous productivity improvement over the last twenty years (as driven by Moore's Law), there remain significant areas for improvement. The lithographic tools in current factories have set the example in productivity improvement. They have evolved from individual tools for vapor prime, coat, expose, bake operations to integrated exposure tools and photoresist tracks that handle wafers sequentially from a load port until they return to the same load port. This paper examines the next logical step in this evolution resulting in the formation of a lithography (Litho) cluster by adding metrology for critical dimension (CD) and overlay measurements and optical inspection. Since with sampling of selected sites and wafers, CD and overlay measurements are relatively quick processes, one or more lithography photocells (exposure tool and photoresist track combinations) could be integrated to one set of centrally located metrology tools. Alternatively, simpler and smaller metrology modules could be integrated into each Litho cluster tool. Since the load ports and robotics could be shared and the total number of metrology tools in the factory is expected to increase dramatically, cost reduction and economies of scale in this combination of tools may be achieved. The benefits are estimated to be a 20% improvement in cycle time and simplified material handling.

SEMICONDUCTOR300 (SC300) is the first pilot manufacturing facility for 300 mm wafers in the world. This company, a joint venture between Infineon Technologies and Motorola, is working on developing a 300 mm manufacturing tool set. The pilot line contains a full compliment of tools for 0.24 micrometer ground rule 64 M DRAM manufacturing. The 64 M DRAM was chosen for the ability to easily benchmark against 200 mm 64 M DRAM manufacturing data from the sister factory. Currently, testing on structures with less than 0.20 micrometer ground rules is occurring the pilot line. In this paper we present the performance of the initial lithography tool set installed at SC300. Several lots of wafers with measurable yield have been produced. These lots have produced data on overlay, critical dimensions, and run-to-run, wafer-to-wafer and within-wafer performance of the various lithography layers. We now have preliminary data on the comparison of 200 mm tools to 300 mm tools in terms of footprint, throughput, reliability, and productivity gains for equivalent square centimeters of silicon. With this data we can start to predict what performance we should expect from 300 mm manufacturing lithography tools.

The presence of HCl during low temperature (790 degrees Celsius - 850 degrees Celsius) wet oxidation process has been shown to cause severe tool corrosion in vertical furnaces. Two types of particulates were observed: white film deposited inside and outside the loading station and metal corrosion at the process door. Although the origin of the white film has not been identified, both types of particles are found to have a direct relationship to the condensed liquid produced during the process. In this study, we evaluated the corrosion causing process and have made modifications to the process as an attempt to resolve the corrosion problem. Three new processes were developed using the same oxidation temperature as the standard HCl/wet oxidation: (1) non-HCl wet oxidation, (2) non-HCl wet oxidation followed by post-oxidation anneal at higher temperature and (3) HCl wet oxidation and high temperature post-oxidation anneal. The anneal step was added as a way to remove acidic condensation. In order to ensure the integrity of MOS devices due to process changes, the end-of- line parameters (Yield, V_t shift and Q_BD) were evaluated. Parametric data showed that the changes do not significantly impact the gate oxide integrity.

In this study, we demonstrate that surface-resist interface interactions are becoming more crucial in DUV lithography as we enter deep into the sub-wavelength era of smaller critical dimension (CD) size and high aspect ratio. This interaction reveals itself as an adhesion reduction of the resist film due to the smaller contact area between the feature and the substrate. Considerable yield improvements in a manufacturing environment can be realized if pattern collapsing of smaller features is prevented by means of proper priming. In addition, next generation photoresist processing equipments must be able to deliver excellent on-wafer results with minimum chemical consumption as environmental health and safety (EHS) requirements are better appreciated in the marketplace. HMDS is not only highly toxic but it is also a prime threat to CD control of most deep ultra violet (DUV) photoresists used for sub-0.18 micrometer design rules. The by-product NH₃ created during priming process with HMDS can neutralize the photo-acid created during the exposure step. There are many technical opportunities in this usually neglected priming process step. In this study, we characterized sub-0.18 micrometer isolated line pattern collapse for UV5 resist on bare Si wafers by using a scanning electron microscope (SEM). The smallest line width printability on wafers primed with different contact angles was analyzed by using both top down and cross section SEM images. Our results show that there is a strong effect of substrate surface and film interface interaction on device yields. More specifically, there is a strong correlation between pattern integrity of features down to 115 nm and vapor prime process conditions. In general, wafers with higher contact angle can support smaller line widths. These results suggest that higher contact angle than the current specification will be required for sub-0.1 micrometer design rule for improved yield. An alternative material to HMDS will probably be needed due to more stringent future requirements and weak bonding characteristics of HMDS. Based on the result of this study, we propose an HMDS consumption reduction scheme for line-widths above 0.2 micrometer. There are many priming-related modular and system level technical enhancements that can be designed in the next generation photoresist processing tools in order to extend 248 nm lithography towards smaller feature sizes.

A chemically assisted physical etching has been developed for the patterning of the Pt electrode with Cl₂/Ar Plasma. Cl₂ plasma performs a very special role which leads to a fence free Pt etching with the highly steep profile. It was found that Pt-Cl compounds on the etch residue were detected by x-ray photoelectron spectroscopy (XPS) and optical emission spectroscopy (OES), which means Cl₂ plasma could generate a chemical reaction during the Pt etching. The hard mask based Pt etch process confirms that a very fine 0.15 micrometer l/s pattern could be achieved with less than 0.05 micrometer CD bias, fence free and the nearly vertical profile. And also, BST capacitors with an optimized Pt electrode shows less than 1fA/cell leakage current at 1 V and it is enough value for the application to 1 Gb DRAM and beyond.

The TiCl4 based CVD-Ti process has been identified as the candidate of choice for the advanced contact metallization. A BKM wet clean recovery (WCR) procedure, involving extended chamber seasoning, has been developed for the CVD-Ti process. The new WCR methodology takes only 5 wafer processing to stabilize the CVD-Ti chamber condition and film properties. It has been found that a chamber seasoning for 200 sec, performed after every idle time (greater than 15 min.) and thermal periodic clean (at wafer count # 200), helps to maintain the CVD-Ti process performance. The reliability of the new chamber operating procedures was validated through a successful 3000 wafer marathon demonstration.

One of the most widespread uses of polysilicon in MOS devices is as the gate electrode for transistors. The gates described in this paper were processed via a two-stage polysilicon deposition. The first deposition stage grew a thin gate polysilicon, which was used as a screen for transistor threshold adjust implants. This was followed by a thick gate polysilicon deposition. All polysilicon depositions described in this paper were deposited in a vertical furnace. It was observed that production wafers in the top position of the polysilicon furnace and directly under dummy wafers displayed unusually high failure frequencies, called functional failures. This is a general failure mode, usually associated with defectivity. Similarities were noted between this failure mode and another failure mode for QBD (charge to breakdown of gate oxide). Both failure modes occurred whenever the production wafers were loaded directly underneath dummy wafers at the thin polysilicon deposition. Atomic Force Microscopy or AFM was used to measure the surface roughness and maximum peak-to-valley height on test wafers that mimicked production wafers. The surface roughness and peak-to-valley measurements were greatest at the top positions of the polysilicon furnace, indicating rougher polysilicon. By removing the dummy wafer directly above the top production wafer, it was found that the production wafers had smoother polysilicon growth. In this paper a mechanism for these functional failures is described that explains the relationship between functional failures and wafer position in the polysilicon furnace. It is demonstrated that when a product wafer is placed under a dummy wafer more silane reacts on the dummy wafer surface than on the production wafer. This is evidenced by the larger RMS surface roughness on the production wafer, as measured by AFM. Production wafers with polysilicon deposited at positions away from dummy wafers had lower RMS surface roughness. During subsequent HF treatments, the HF etched the valleys and underlying gate oxide, which produced oxide pinholes and caused the functional failures.

In the photo process, the defect of developer residue on wafer backside is always negligible. Such as figure 1 is the photographs of residue defect onto wafer backside, this defect is easy to induce some problems such as a wafer transfer error, chamber particle in the etcher machine and rework issue for cleaning wafer backside. In this paper, we provide serval methods to prevent the 'developer residue on wafer backside issue' reoccurrence. Specially the clean effect of wafer backside of developer process had to be improved effectively, the effective clean method include the gap (distance) be optimized from the knife edge to wafer backside with the various film (Silicon; Nitride; Poly: TEOS; PESIN film) and the liquid drain port of developer machine had to be modified to reduce the remained liquid that is absorbed onto wafer backside.

The trench formation is important process in isolation of circuits in submicron devices. The sharp bottom corners in trench can cause undue stress during subsequent furnace cycle and may become the cause for dislocation formations. Dislocations cause leakage in devices and yield loss. Isotropic profiles of trench may cause problems in filling of oxide in trench. Bottom rounding of trench is desirable for stress reduction and leakage reduction. In this paper SF6 and C12 plasma along with other process parameters are explored to obtain bottom corner rounding. It was found that SF6 and C12 plasma etching was able to produce bottom corner rounding in all cases where as conventional C12 and HBR and other similar anisotropic etch processes produced sharp bottom corners. Etch rate and hardmask removal rate was compared with new process and was found to be comparable to conventional HBR and C12 chemistry. Defects formation related to trench chemistry was also compared using metrology equipment like KLA2132. Etch rate and bottom rounding was also compared with respect to radial and circuit density dependence. Scanning Electron Microscopy method was used to obtain all related trench profiles.

We demonstrate an approach to cross-section and measure sub- 0.25 micrometer photoresist profiles in both a manual and an automated fashion. This approach includes the use of a focused ion beam (FIB) system to cut small trenches through photoresist lines, leaving a clean, vertical face to measure. We demonstrate the advantage of using this process over existing techniques in the semiconductor industry. A FIB can locally cross-section the photoresist, resulting in a side- wall that is comparable to that of a mechanical cleave. It can then measure the profile of the photoresist at multiple points using a 5 nm gallium probe. The system accomplishes the entire process inside one vacuum chamber with a limited number of steps. In contrast, when using a SEM to measure profiles, the sample must be mechanically cleaved outside of the vacuum chamber, potentially destroying the entire part and leaving a slightly distorted viewing face. Also, a SEM probe can cause swelling of the photoresist due to higher currents and penetration depths than a FIB probe and must therefore be used at low accelerating voltages. When operated at these low accelerating voltages, the SEM has degraded resolution with a spot size near 10 nm. A scanning probe microscope (SPM), on the other hand, can non-destructively measure profiles, but it is slow and less automated than the FIB or SEM. Unlike a FIB, the SPM lacks the ability to image the material transition directly beneath the photoresist. We also address concerns of sample damage, gallium contamination, and image quality.

High Density Plasma (HDP) deposition provides a means to deposit high quality dielectrics meeting submicron gap fill requirements. But, compared to traditional PECVD processing, HDP is relatively expensive due to the higher capital cost of the equipment. In order to keep processing costs low, it became necessary to maximize the wafer throughput of HDP processing without degrading the film properties. The approach taken was to optimize the post deposition microwave in-situ clean efficiency. A regression model, based on actual data, indicated that number of wafers processed before a chamber clean was the dominant factor. Furthermore, a design change in the ceramic hardware, surrounding the electrostatic chuck, provided thermal isolation resulting in an enhanced clean rate of the chamber process kit. An infra-red detector located in the chamber exhaust line provided a means to endpoint the clean and in-film particle data confirmed the infra-red results. The combination of increased chamber clean frequency, optimized clean time and improved process.

EndPoint Plus (EPP), a remote PC-based endpoint system, coupled to a Lam Research Corporation 200 mm Rainbow 4520 dielectric etch system, reliably detected etch endpoints of low exposure area (less than 3%) dielectric films. A narrow- bandwidth sampling of etch plasma emission spectra is monitored and processed to enhance detection of small spectral changes associated with the elimination of an etched film. Reliable and repeatable endpoint markers of low exposure, multi-layered films is demonstrated during a mini-marathon in a production environment.

We developed a downflow asher which incorporates a large-sized microwave excited plasma source with a slot antennas, for 300 mm wafers. An ashing rate of 4.5 micrometer/min and uniformity of plus or minus 5.1% were obtained at a wafer temperature of 250 degrees Celsius. The ashing rate was approximately fourfold and the uniformity level was similar to those obtained with conventional downflow asher. The newly developed asher incorporates: (1) a high-density plasma source with slot antennas, (2) a processing chamber the shape of which is optimized by gas flow simulations and (3) a compact, high- speed wafer transportation system with an originally developed vacuum robot which is primarily responsible for the high ashing rate. The maximum overall throughput, including that of the transportation system, is 160 wafers/h. Application of this system to the ashing of 300 mm wafers is expected.

The technique of investigations of resistance (rho) , thermoelectric power S, and galvanomagnetic properties of materials by the two-terminal method of measurements under pressure up to 30 GPa is discussed. The combine of stationary and nonstationary regimes of treatment, variation of high pressure chambers with conducting or insulating plungers and using of simultaneous and parallel measurements of various properties are proposed to estimate the parameters of materials under testing. The results of investigations of initial semiconductor and high pressure metal phases of Ge, Te, and molecular solid-Iodine up to 30 GPa at the diamond- plungers apparatus are represented. The technique may be useful for semiconductor fabricated device treatment.

Of the various techniques used to monitor wafer temperature during hot metal sputter deposition, use of wafers with Ti/Al alloy film stacks provides high consistency, run-to-run repeatability, good temperature sensitivity, and ease of use in a production factory. This work details the development of improved Ti/Al temperature monitor wafers for use on hot metal physical vapor deposition (PVD) systems. Various combinations of (1) Ti, TiW, and AlCu alloys, and (2) varying thickness of each metal layer were ran at three different heater temperature setpoints on an Applied Materials Endura 5500 PVD system. The experimental design is discussed and the temperature sensitivities are analyzed for each Ti/Al film stack combination and subsequently compared to the standard Ti/Al alloy monitor performance. The correct combination of AlCu film alloy and AlCu film thickness resulted in a monitor three times more sensitive than the existing Ti/Al monitor.

A multi-step high density plasma etch process, based on chlorine and sulfur hexafluoride chemistry (SF₆), for LRC single wafer metal etcher was developed, characterized and optimized to anisotropically etch the metal stack which consists of a thin titanium tungsten ARC, hot deposited aluminum copper over titanium tungsten. The titanium tungsten used in the metal structure presents unique constraints on etch selectivity to underlying film while simultaneously requiring clearing metal stringers. The etching was further complicated by lateral etching of aluminum copper (AlCu) during titanium tungsten (TiW) etch and overetch steps. With the help of design-of-experiment techniques, multi-variable factorial experiments were conducted to determine the optimum processes for the bulk metal etch, barrier metal layer etch and overetch steps. Characterization parameters include the metal etch rate, etch selectivity, CD line-width, metal resistance and plasma charging damages. Special attention was paid to the overetch window since the metal quality is very sensitive to the overetch conditions. Insufficient overetch may leave metal stingers or metal shorts. Excessive overetch may cause severe CD undercutting and great loss of TEOS oxide under-layer.

The lithography process for 0.25 micrometer metal masking faces the challenge of tight design rule. Island patterning and line-end shortening have become more important due to the zero or small contact/via enclosure. A full understanding of the process latitude is necessary to choose the right process for a certain metal layer of 0.25 micrometer technology. In this paper, we develop a methodology to evaluate and optimize a metal asking process based on a set of critical structures. By characterized the overlapping process window for these critical structures, a comprehensive process latitude can be defined. This methodology is applied to the optimization of stepper NA/PC setting and the selection between I-line and DUV processes.

As process controls tighten in the semiconductor industry, the need to understand the variables that determine system performance become more important. For plasma etch systems, process success depends on the control of key parameters such as: vacuum integrity, pressure, gas flows, and RF power. It is imperative to baseline, monitor, and control these variables. This paper presents an overview of the methods and tools used by Motorola BMC fabrication facility to characterize an Applied Materials polysilicon etcher. Tool performance data obtained from our traditional measurement techniques are limited in their scope and do not provide a complete picture of the ultimate tool performance. Presently the BMC traditional characterization tools provide a snapshot of the static operation of the equipment under test (EUT); however, complete evaluation of the dynamic performance cannot be monitored without the aid of specialized diagnostic equipment. To provide us with a complete system baseline evaluation of the polysilicon etcher, three diagnostic tools were utilized: Lucas Labs Vacuum Diagnostic System, Residual Gas Analyzer, and the ENI Voltage/Impedance Probe. The diagnostic methodology used to baseline and match key parameters of qualified production equipment has had an immense impact on other equipment characterization in the facility. It has resulted in reduced cycle time for new equipment introduction as well.

There has been a great demand for improved end point detection techniques for advanced etching of III-V ternary multi stack layers. Current etch rate and end point monitoring techniques are based on three methods. The first is to use timed or a blind etch as it is known, this offers no monitoring of the etch process. The second is to use optical emission spectroscopy (OES) which is a secondary measurement of the process and requires a large open area, fast etch rate, and a detectable emission line from the etch products. The third is laser interferometry, a primary measurement, based on light interference of reflected beams from several layers in the stack. Up to now the use of commercially available interferometric techniques has not permitted the measurement of etch rates and end point the etch processes due to the absorption of the wavelengths of light available in current process control systems. A new in-situ end point system utilizing a 905 nm laser interferometer will be described that allows the ability to follow dry etching of III-V ternary multi stack layers. End point detection techniques on various Al_xGa_1-xAs layers on GaAs with varying compositions (i.e. X equals 0.3 - 0.92) and different types (n- or p- AlGaAs) are examined.

The yield of an oxide isolated bipolar technology was substantially enhanced by changing the photolithography processing at the isolation layer. Changing the exposure bias improved the Cpk by 25% and the yield by 6%. Changing to a different develop chemistry eliminated corner defects and substantially reduced fallout for leakage. Corner defects are correlated to microgrooves and protuberances in the photoresist profile. In this paper, the mechanism for the yield improvement is explained.