The reduction of yield loss caused by particles is a key topic of productivity enhancement. It deals with many components of a fab's structure: (1) Cultural mindset of managers, engineers, and operators -- to have champions for that mission, (2) selection of defect metrology tools -- with high throughput and reliable data, (3) single equipment characterization -- to set challenging specs according to the best performing tool, (4) inline reaction procedures -- to transfer knowledge and responsibility to the operators, (5) statistical evaluation of large datasets -- including correlation to electrical yield, (6) and to trace back the way to the single tools or the low performing processes. This paper discusses some topics to be considered during process and equipment planning, ramp up, and mature production. It has been proven to be successful during a very aggressive ramp up in wafer starts and an even more convincing yield increase of a fab, that now started the production of DRAM's in quarter micron technology. It will conclude in an understanding, that besides a reliable statistical methodology the human performance is the key: can we really integrate people of different groups and levels of responsibility and motivate them to take joint actions for yield goals?

Historically, a number of in-line particle measurements have been performed on separate test wafers included with product wafers during polysilicon processes. By performing film thickness and particulate measurements directly on product wafers, instead, a number of benefits accrue: (1) reduced test wafer usage, (2) reduced test wafer storage requirements, (3) reduced need for equipment to reclaim test wafers, (4) reduced need for direct labor to reclaim test wafers, and (5) reduced engineering 'false alarms' due to incorrectly processed test wafers. Implementation of on-product measurements for the polysilicon diffusion process required a number of changes in both philosophy and methodology. We show the necessary steps to implementation of on-product particle measurements with concern for overall manufacturing efficiency and the need to maintain appropriate control. Particle results from the Tencor 7600 Surfscan are presented.

This paper investigates the use of in situ particle monitors as a means of yield enhancement and wafer cost reduction, for a fab which has upgraded its tool set and technology during the previous two years. As the new technologies were introduced and we reached the entitlement of the available tool set we found that 50% of the yield limiting causes were directly attributed to particles introduced during process. We describe here two ISPM projects with AMAT 8330 and MRC Eclipse. We discuss the baseline established during normal operation for AMAT 8330, comparing it with traditional methods of particle measurement, the particle trending between wet cleans, in order to establish the effectiveness of these cleans. With the ISPM it was possible to identify the most contaminating processes and correlate the yield loss when particle amount was high. Using the ISPM we identified the influence of the type of wet cleans as well as of the process pumping steps and showed that yield could be improved if the ISPM counts were reduced. A similar exercise done with the MRC eclipse did not give us any significant correlation with our present monitors and so the project was stopped for lack of usefulness of the ISPM monitor.

Particles from the Lam 4400 blocked the etching of nitride and silicon during the trench etch for semi-recessed LOCOS field oxidation. This trench etch resulted in poor mean time between cleans (MTBC) of less than 500 wafers, reduced availability of the system, wafer scrappage up to 2.5%, and masked KLA defect source analysis at subsequent steps. EDX analysis of the particles showed them to be AlF_x, the source of which we determined to be the Al chamber parts reacting with the F plasma. This unique paper shows the benefits of various improvements to plasma cleans, chamber cleans, and equipment hardware upgrades (such as DI water sealed, anodized chamber parts). We compare the performance of the tool before and after the improvements, resulting in a 10 fold increase in MTBC, 20% increase in system availability, 15X reduction in particle defect densities, and resultant zero wafer scrappage due to blocked trench etc. Detailed system performance data (MTBC, availability, particle data), KLA defect trend charts, and SEM/EDX data is presented.

The measurement of particle size and concentration in Di-water and various chemicals has permitted us to verify the performance of more high sensitivity sensors. The size of these particles have been determined by specialized instrumentation. The paper presents the comparison results of sizing accuracy and concentration measurement for ultrapure liquids. The results of sizing accuracy as shown for sensors due of light scattering for latex spheres in Di and silicon spheres in chemicals. The concentration measurement (particles/100 ml) made with more sensors against factor leads to identify which sensors are sensitive in Di water and which in chemicals and permit the measurement of their sensitivity and the counting efficiency too. The study permitted the best results for measurement of Di and ultrapure chemicals for particle counting and sizing recommended for all minielectronics fabs.

This paper provides several guides for solving or reducing metal defect from sputter stage, photo stage and etch stage. Particles from three stages were detected with KLA inspection and EDX component analysis tool. According to all evidence, the final results point out the criteria of various type defects in this paper. Specially, in our experiment, we get some obvious results, such as solving the resist gel mechanism in TEL coating track; reducing the splashing particle defect in TEL developer track; reducing particle for the new cleaning method in etching machine (dry 8330); reducing particle during the wafer transferring from ADI (photo) to AEI (etch).

A radio frequency (rf) sensor has been used to monitor and characterize processes and to support real time control of deposited power in a Lam Research Corporation TCP 9600SE metal etching system. This etcher has separate power supplies for the TCP source power that generates the plasma and for the bias power at the wafer surface. The rf sensor was installed only in the bias power circuit between the matching network and the chamber. It was found that in open loop mode, where only the generator output was controlled, the efficiency of the rf system was significantly less than unity, and it varied with changes in either process or chamber hardware. These losses can be accounted for mainly by losses in the matching network and a simple relation was found between the overall efficiency and the resistance of the load. Closed loop control based on the sensor output was found to compensate well for these effects and to give better defined and better controlled power deposition.

Reactive ion etching (RIE) is commonly used, as a process tool, for the etching of polysilicon, silicon dioxide, silicon nitride and other thin film deposits. One of the key requirements of the etching process is the accurate end-point detection of the process. There exist a number of process monitoring techniques for end-point detection, these however are costly to install and maintain. In response to this requirement, a new method for end-point detection of polysilicon topography etching in single wafer plasma reactive ion etcher is presented here, which incurs no added costs. The method is based upon experimental results correlating polysilicon etching end-point with the increase in the cathodic self-bias voltage developed across the substrate. It is shown that the end-point of polysilicon topography etching can be found by monitoring the first derivative of the self- bias voltage with time. Using this method it has been demonstrated that accurate end-point detection of polysilicon etching can be obtained with a residue free field, near- vertical polysilicon profile and critical dimension loss of less than 0.05 micrometer.

This paper presents results from a prototype scatterometer which show that distinctly different zeroth-order diffraction signatures are produced for wafers processed under different etch conditions. We present comparisons between the profiles estimated using the scatterometer signatures and those measured using atomic force microscopy, in-line scanning electron microscopy, and cross-sectional scanning electron microscopy. We found that all the metrology techniques investigated provided useful information about the profile characteristics, but only the atomic force microscope and the scatterometer are suitable as in-line measurements of critical dimension profiles -- and only scatterometry provides estimates of the underlying film structure. In this study, the wafers consisted of patterned photoresist over blanket layers of a deep-ultravoilet anti-reflection coating, polysilicon, and silicon dioxide. These wafers were intentionally varied at the lithography step and intentionally misprocessed at the gate etch step to produce a wide range of process variation. Scatterometry measurements were made on multiple dies per wafer and estimates of feature profile information such as film thickness and critical dimension were generated by comparing the experimental signature to a library of theoretical solutions. We found that the scatterometer was capable of showing signal differences for different wafer processing conditions, and can be used as an in-line measurement of profile characteristics suitable for closed- loop process control of lithographic and etch processes.

A more robust chlorine chemistry based reactive ion etch (RIE) process was developed, characterized and optimized to anisotropically etch the interconnecting metal layers for use in the fabrication of CMOS and BiCMOS IC devices, using the Lam 4600 single wafer etcher. The titanium nitride and titanium silicide buried layer, used in the metal 1 structure, present unique constraints on etch selectivity to the underlying film. The process must clear metal stringers with minimal lateral etching of the aluminum during the tiN/Ti etch and overetch steps. The new optimized process meets all requirements imposed by advanced technologies, such as vertical metal sidewalls, wide process latitude, tight CD control, minimal of TEOS oxide underlayer, less sensitivity to photoresist pattern, excellent reliability and reproducibility, and lower level of polymer (reaction by- product) build-up in reactor chamber which could lead to metal corrosion and cluster defects.

Chemical mechanical polishing (CMP) of silicon oxide interlayer dielectric is a critical process in modern multi- layer metal integrated circuit manufacturing. In this process, the rate of planarization of features on a silicon wafer surface changes with age of the polishing pad. This effect creates the need for adjustment of polishing times to compensate for changes in planarization rates. The way that planarization rate varies with polish time must be defined to develop robust control of this process. In this work, a theoretical model for the dependence of planarization rate on polish time was developed. This model was then applied to data from a Westech 472 CMP system and shown to accurately capture the time variation of measured removal rates. A control algorithm using this model was tried using a different CMP tool, the Westech 372, creating a mismatch between the control model and process. Nonetheless, the control model quickly adapted to the new conditions and controlled the process well.

Optical emission spectroscopy (OES) data for 495 wavelengths and wafer measurements (pre- and post-oxide film thickness) from a commercial etch tool were collected for 18 oxide wafers to explore the feasibility of using OES as an in-situ sensor to estimate average oxide etch rate. A variable selection method is proposed based on the principle of partial least square (PLS) regression, which select several most informative wavelengths to build ordinary least square (OLS) regression models. Compared with the PLS models, it is found that OLS regression models based on selected wavelengths are more robust.

The remote plasma-enhanced chemical vapor deposition (RPCVD) system is an experimental low temperature Si/Si-Ge epitaxy system. This paper describes an integrated hardware/software automation package developed for the RPCVD system. Aspects of the system controlled by the package include pneumatic gas valves, mass flow controllers (MFCs), and a temperature controller. The package was developed on an Apple Quadra 950 platform using LabVIEW^TM 3.1 and associated data acquisition and control hardware supplied by National Instruments and other vendors. The software interface allows the user to operate the system through a virtual control panel which displays critical system parameters such as chamber pressure, chamber temperature and gas flow rates, along with the states of the gas valves and the MFCs. The system can also be run in the recipe mode, in which a sequence of steps are read in from an Excel^TM file. A simulation routine scans each recipe for possible errors such as violation of valve interlocks while the recipe is being loaded. All actions, whether in the manual mode or the recipe mode, are recorded in a log file. Finally, since many of the gases used in the RPCVD process are toxic and/or flammable, there is an emphasis on safety in the entire control scheme. A safety monitor routine constantly checks for valve interlocks and pressure-valve interlocks. Upon detecting an illegal state, it automatically takes necessary action to bring the system into a safe state. In addition to these software safety features, there are also hardware interlocks to deal with such situations as power outages.

This paper describes the development of a standard diffusion recipe model and its use within a numerical optimization method to obtain time-optimal diffusion recipes, within nonlinear temperature-dependent constraints. The diffusion model and optimization program have been packaged as a diffusion process engineering tool, which can be applied to optimize existing diffusion recipes, thereby reducing processing time in production. Equivalence of diffusion recipes is demonstrated using commercial diffusion simulation software, on both unoptimized and optimized recipes.

For the past few years, both academia and industry have increased research in run-to-run or supervisory level control of semiconductor processes. Run-to-run control has been cited as a necessary and integral part of many current and future leading edge processes. Run-to-run control has been applied or proposed for common and critical fab processes such as chemical mechanical polish (CMP) and lithography/etch line width control. Many traditional as well as advanced control techniques have been used in the formulation of run-to-run controllers (time series and statistical process control- based, state space methods, simple P/PI/PID algorithms, model- based predictive control, etc.). In addition, papers have been published that discuss some of the many issues involved in deploying a run-to-run controller. However, one important issue that affects deployment of run-to-run control has largely been ignored. In many state-of-the-art fabs, especially those that manufacture microprocessors and other logic chips, costly fab tools are required to run more than one process for throughput and flexibility reasons. Furthermore, today's fabs frequently produce more than one type of chip. Both of these factors, multi-processing and - products, sometimes lead to major difficulties in designing and deploying a run-to-run controller This paper focuses on the issues involved in multi-product and -process run-to-run control, as well as compare and contrast some strategies that could be used to design a run-to-run control system under these circumstances.

Absence of a good resist selectivity is a key issue in the metal etch. It becomes increasingly critical when the geometry shrinks below the sub-half micron and the resist thickness reduces further for lithography to get smaller features resolved. Measured values are often quoted based on various techniques like surface profiler or cross section analysis, etc. For a multi step etch recipe we analyzed step by step the etched photoresist cross section for feature sizes between 0.40 . . . 0.65 micrometer and bondpads by using a scanning electron microscope (SEM). We found that the real photoresist margin is independent on the feature size which we explain using a simple geometrical model. However, this value is remarkably smaller than the height of the remaining photoresist on top of the center part of a bondpad measured using a surface profiler. Subsequently, the profiler measurements result in selectivity values which are considerably higher than those measured at small features with cross section SEM analysis. We discuss advantages and limitations of profiler measurements. The comparison between the results of both methods open the possibility to utilize the advantages of surface profiling (e.g. non-destructive approach) by reducing the risk to get overestimated selectivity values for small features. This method is very useful in metal etch process development and forecasting the requirements for the future technology as well as to interpret absolute selectivity often quoted.

The polysilicon process had a problem with 15% higher average class probe sheet resistance on wafers running in the top furnace position at gate polysilicon and receive 'sandwich' polysilicon (thin poly deposition followed by gate poly deposition), than wafers that run in center and bottom of the furnace. The higher sheet resistance is caused by a thicker intrapoly oxide that grows between the thin polysilicon and the gate polysilicon on wafers in the top furnace position. By increasing the push speed from 25 minutes to 5 minutes and increasing the N2 purge during push, the intrapoly oxide was minimized and the class probe polysilicon sheet resistance distribution was tightened by over 50%. The fast push process also tightened the linear N-channel threshold voltage distribution by approximately 10%.

Five years ago, factory automation (F/A) was not prevalent in the fab. Today facing the drastically changed market and the intense competition, management request the plant floor data be forward to their desktop computer. This increased demand rapidly pushed F/A to the computer integrated manufacturing (CIM). Through personalization, we successfully reduced a computer size, let them can be stored on our desktop. PC initiates a computer new era. With the advent of the network, the network computer (NC) creates fresh problems for us. When we plan to invest more than $3 billion to build new 300 mm fab, the next generation technology raises a challenging bar.

The need for cost reduction and flexibility in semiconductor production will result in a wider application of computer based automation systems. With the setup of a new and advanced CMOS semiconductor line in the Fraunhofer Institute for Silicon Technology [ISIT, Itzehoe (D)] a new line information system (LIS) was introduced based on an advanced model for the underlying data structure. This data model was implemented into an ORACLE-RDBMS. A cellworks based system (JOSIS) was used for the integration of the production equipment, communication and automated database bookings and information retrievals. During the ramp up of the production line this new system is used for the fab control. The data model and the cellworks based system integration is explained. This system enables an on-line overview of the work in progress in the fab, lot order history and equipment status and history. Based on this figures improved production and cost monitoring and optimization is possible. First examples of the information gained by this system are presented. The modular set-up of the LIS system will allow easy data exchange with additional software tools like scheduler, different fab control systems like PROMIS and accounting systems like SAP. Modifications necessary for the integration of PROMIS are described.

Many steps in the manufacturing of semiconductors offer no opportunity for real-time measurement of the wafer state, necessitating the use of pre- and post-process measurements of the wafer state in a run-to-run control algorithm. The predominant algorithm in the industry is an extended form of SPC using an EWMA filter to adjust a model parameter vector using the available measurements. This paper evaluates the merits of using an optimal discrete controller relying on a discrete-time constrained state-space process model that incorporates feedforward action using the pre-process measurement and feedback using the post-process measurement, accounts for the process statistics using a noise model and optimal filtering theory, and ensures integral action in the controller by estimating unmeasured disturbances. Comparison to the EWMA algorithm are presented using simulations based on actual plant data from a chemical-mechanical polishing application. The polish process is particularly suitable for the application of such a controller because of the natural method the controller provides for incorporating unmeasured disturbances, like pad and slurry changes, in the control action.

To improve lithographic process throughput, it has become a general trend to link coater, stepper, and developer to an integrated PHOTO cell. In fine photolithography, TARC (top anti-reflective coating) is utilized intensively to obtain better CD (critical dimension) control. However, the coating of photoresist and TARC is not performed successively. A baking step about 90 seconds is employed in between these two coating steps. Throughput is thus affected and coating step becomes the bottleneck of whole lithography process. A series of experiments were investigated to coat TARC right after photoresist coatings. Results show that throughput was greatly improved. But for certain TARC and photoresist pairs, resist scumming due to inter-mixing of these two chemicals was found after exposure and developing. In some cases, the coater drain piping was stuck by the occurrence of precipitation resulted from the interaction between TARC and photoresist. To prevent this event from happening, precipitation tests of TARC and photoresist are investigated. Experiment was performed by adding TARC to photo resist with/without dilution by thinner. The occurrence of precipitation was observed. Seven kinds of photo resist and three kinds of TARC, provided by different vendors, are studied at different volume ratios on these tests. Results show that the lower photoresist to TARC ratio is, the more precipitation formed. Adding thinner, affecting the precipitation in different ways, induces more precipitation in most cases and cause the precipitation to disappear in some systems. One TARC is found to be inert to most photo resists. Photo resists with higher viscosity turn to gel when interacting with TARC.

The SiH4 gas injectors were having a problem with early breakage in vertical polysilicon deposition furnaces. The quartz tube employed in some vertical thermal reactors uses a quartz injector to deliver process gas to the bottom zone of the furnace. This injector extends down from the top dome of the quartz tube. Polysilicon deposition occurs on the inner and outer surfaces of the injector. The difference in the coefficient of expansion between the silicon and quartz in conjunction with the normal temperature gradients seen in the furnace results in unpredictable injector breakage. The authors provided the initial concept for a removable injector and worked with a quartzware and silicon carbide supplier to develop the injector design from silicon carbide (SiC). Silicon carbide has a comparable thermal expansion coefficient compared with polysilicon thereby eliminating the possibility of early injector breakage. The strength, purity and extensive usage of silicon carbide in the semiconductor industry made SiC an ideal candidate as an injector.

Results on electrical characterization of test structures with fluorosilicate glass (FSG) deposited in four different chemical vapor deposition (CVD) tools are reported. Data demonstrate high sensitivity of the electrical properties of FSG to metal pattern density. Both dielectric constant and leakage current are shown to be critical parameters for evaluation of dielectric performance.

Alkali contamination in dielectric oxides has been a critical issue during the shrinking of integrated circuit devices. Identification and monitoring of ionic contamination is typically done with secondary ion mass spectrometry (SIMS). Improvements in the sampling procedure and analysis of the SIMS data was accomplished during this study. The identification of tools, processes, or materials that cause the ionic contamination and the resultant corrective actions to effectively lower the contamination in the circuit was done, and an improvement of over 3 orders of magnitude was accomplished. An ionic contamination reduction technique that can be done following an analysis of mobile ion concentration and location on, or within, the dielectric oxide films is discussed. Characterization of the clean process parameters that contributes to contamination removal was done, as well as particle and defectivity reduction by process and equipment optimization.

Monitoring techniques were used to analyze metal lithography corrosion on post-metal etch processes and after solvent processing. Liquid ion chromatography (LIC) techniques were used to monitor the chlorine ion concentration on the wafers following plasma metal etch processing, and energy dispersive x-ray spectroscopy (EDS) techniques were used to monitor the level of fluorine ions which prevented native oxide growth that protects the metallization from solvent damage. Characterizations were run to identify the significant integrated circuit process factors and environmental conditions that increased the corrosion occurrence or severity above the baseline level. Monitoring of the environmental corrosion risk was done with LIC and air quality monitors. Wafer processing and substrate factors significant to corrosion occurrence were: (1) underlying oxide type, (2) photoresist type, (3) pattern density of the metal geometries, (4) metal etch wafer position, (5) connection to substrate by vias/contacts, (6) humidity, (7) backside condition of the wafer, (8) overetch step chlorine flow, and (9) metal thickness, in increasing significance. Significant reduction in measured corrosive ion levels and observed corrosion defects was obtained with modified processing schemes.

An ICP spectrometer was modified to sample both gaseous and liquids in a controlled format. The gas proportioner was characterized and the ICP sample flow rate was adjusted to prevent negative effects on the plasma profile. Spectra comparisons were done using Ar to compare the effect of sampling techniques. The comparison of spectra from the ICP and the plasma etch tools from simple gas mixtures resulted in similar atomic spectra, although the spectral intensity distribution differed. Characterizations were done on moisture contamination, additive gas effects, loading effects, ionic dopant levels, and metallic silicide films. As the samples became more complex, the resulting spectra differences between plasma sources became less similar.

The focus window of various topographies and substrate (borophosphosilicategass, plasma enhanced oxide and Al/Si/Cu) is discussed in this paper. Also the electric test data and Cp yield with different focus are introduced. Finally, the usable depth of focus, auto focus system and simulation model are applied to describe the difference between machine and process best focus.

A unified approach to the modeling, simulation, and control of thin film processing is presented. The focus of this approach is to combine in-situ sensing with a model that deals directly with evolving surfaces. Using this method, and an in-situ process modeling technique (e.g., plasma emission spectroscopy during reactive ion etching) is used as a source of in/out data for a model which deals exclusively with interface evolution. In this way, in-situ monitoring gives predictive process control capability, rather than simple end-point detection.

The diamond-plungers apparatus for simultaneous measurements of resistance (rho) , thermoelectric power S, volume V of samples is described. The apparatus contains the microcontroller for the operation by the measurements and keeping the experimental data. The examples, comprised S, (rho) , V recording for semiconductors Ge, Si and HgTeS in pressure range 0 - 30 GPa are represented.