This PDF file contains the front matter associated with SPIE Proceedings Volume PMJ19, including the Title Page, Copyright information, Table of Contents, Author and Conference Committee lists.

FPGA (Field Programmable Gate Array) has been continually growing – expanding functionality, improving powerperformance and enlarging capacity, in past several decades. Moore’s Law has been gradually slowing down and technology becomes more expensive in past several nodes. However with continual architecture, design and technology innovations, FPGA’s capacity expansion continues, beyond Moore’s Law. 3D-IC, embedded processing SOC, HBM integration, RF-SOC and furthermore, coming Versal ACAP (Adaptive Compute Acceleration Platform) family, ensures more and more suitable applications in data centers, machine learning (ML), 5G, automotive and many other applications in coming years.

A new lithography optics designed and fabricated for printing 300-μm patterns on inside surfaces of pipes with an inner diameter of 10 mm and a length of 300 mm was investigated. Such patterning is required for giving textures to heat pipes, graving bearing grooves, and fabricating electrode and wiring patterns on inside surfaces of pipes. Although the pattern size is far larger than those used for semiconductor device fabrication, patterning onto non-flat surfaces in narrow spaces has hardly been researched anywhere else. Here, a linear optical fiber array composed of 500-μm fibers with squared ends were used for leading exposure light from light emitting diodes and designating pattern shapes. Then, the fiber array end was contacted to the inlet of a taper-conduit, and the pattern shapes were reduced in 1/2.25 at the outlet of the conduit. The conduit was composed of densely contacted fine optical fibers, and each fiber diameter was gradually reduced in the longitudinal direction keeping each fiber position invariably. The reduced pattern shapes were projected by a ratio of 1.25/1 using a simple convex lens on the inside surface of a pipe. Here, the performances of the projection optics were investigated by printing patterns on wafers used temporarily in place of the inside wall of a pipe. As a result, hole and linear space patterns with sizes or widths of approximately 300 μm were successfully formed.

In this report, we will describe the progress of our new SOC material development for the underlayer. In the advanced patterning technology such as EUV lithography, the etching resistance and the adhesive property with a middle layer will be key requirements as well as the planarization. We designed new polymers for SOC material that were improved the etching resistance toward next generation patterning technology on the basis of Ohnishi parameter as a guideline of the polymer design. The etching resistance of our newly developed polymers were about 1.7 times and 1.5 times stronger than the polymer A we reported previously and the PHS or novolac. The adhesive property was evaluated by measuring water contact angle and the water contact angle of our newly developed polymers were similar to the novolac. This result indicated that the developed polymer showed similar hydrophilicity to the novolac with keeping higher O₂ etching resistance than novolac.

FSCE focused on resist materials and coordinate correction technology for FPD mask and carried out research on underlying technology. The results we obtained are reported.

Over the past years, ASML has taken the NXE pellicle concept (2015) from the concept level to pilot production (2016) and subsequently to a final product (2017 and onwards). In this paper we will show the progress in pellicle development that was made over the past year. After ASML started volume production of pellicles with the previous film generation, a new film generation was introduced end 2018. This new generation of pellicles shows considerable improvements in imaging performance, stability, EUV power capability and EUV reflectivity. The current generation of pellicle films show an EUV power capability of 250 Watts; improvements were also made in the imaging performance, where the EUV reflectivity of the pellicle reduced to below 0.04%. The EUV transmission of the latest pellicles increased to 83%.

The mask is a known contributor to intra-field fingerprints at the wafer level. Traditionally, a 3σ distribution of critical dimensions (CDs) on mask was considered sufficient to characterize the contribution to the CD distribution at wafer level. Recent studies report wafer local CD distributions characterized for statistics beyond 3σ¹. Mask has been shown to contribute to wafer local CD distribution also which is typically quantified as Local CD Uniformity (LCDU), a 3σ metric². Additionally, the local placement distribution on wafer could be a contributor to Edge Placement Error (EPE)³. Consequently, it is imperative to understand, characterize and ultimately control the mask contributions to local CD and placement distribution at wafer level. This work is an investigation of local CD and placement distribution on an EUV mask and its impact on distributions at wafer level.

Mask Process Correction (MPC) is becoming increasingly relevant as the industry moves toward more challenging technology nodes. Because running MPC on large layouts can be extremely resource intensive, it is important to strike a balance between the quality of the correction and the total turnaround time (TAT). This paper describes the results of applying a geometry-based MPC solution to a mask lithography process created at Toppan where the model is calibrated from AEI metrology data of patterns that accounts for beam blur, etch, and proximity effects present in the etched mask up to ~1 um. In this solution, the model calibration can result in different but equivalent predictors, i.e., the model parameters can differ while the overall error residuals (model RMS) can be nearly identical. The following sections probe a possible trade-off between correction quality and speed by testing how an MPC software based on edge movement behaves as the effective range of an enhanced multi-Gaussian mask model template is constrained.

It has been known for quite a long time that the best possible process window obtainable for 193i layers is by using ILT correction. These are typically converted (at a high runtime cost) to Manhattan masks both for reasons of mask manufacturability as well as computational efficiency; OPC M3D and rigorous simulators have, until very recently, been optimized for speed to run primarily with Manhattan shapes. We have recently shown that the insertion into production of multibeam mask writers makes writing curvilinear masks possible and that it is preferable to move toward a completely curvilinear paradigm, not only because the ILT is better, but because the mask manufactured will have reduced variability. Recent studies have shown a similar need for ILT-style corrections for EUV, mainly due to more complex thick mask effects. We extend the work using Monte-Carlo methods for mask variability to show that EUV layers more strongly require curvilinear approaches to mask writing in order to minimize the wafer PV bands due to both the tighter overall tolerances combined with the smaller wavelength (13.5 vs, 193) which transfers mask defects to wafer over smaller lengthscales.

Deep Learning (DL) is one of the most exciting fields in artificial intelligence (AI) right now. It’s still early days, but DL will completely change the lithography and photomask industry to automate or optimize the efficiency of equipment and processes. The key element required for building applied DL is a GPU-accelerated simulation environment. In this paper, we will present a Deep Learning Kit (DLK), an artificial intelligence platform that allows semiconductor manufacturing companies and mask shops to do such simulations for DL training, and show a case study with DLK. DLK provides accurate physical models for masks and lithography that are fully accelerated by CUDA on GPUs, the de facto DL training platform, a GPU accelerated Computational Design Platform (CDP), fully integrated and distributed TensorFlowTM on CDP, and pre-trained neural network models for wafer and mask problems. Using DLK, semiconductor manufacturing companies and mask shops can quickly build their deep neural network model, connect the simulator of their choice (either provided by D2S or its partners), and train the neural network model in that environment to learn a desired behavior.

Prototype of Massively Parallel Electron Beam Write (MPEBW) system was developed for mask less lithography. A 100×100 array of nanocrystalline-silicon (nc-Si) electron emitter is controlled by an active matrix driving LSI. The LSI receives external writing bitmap data, and switches 100×100 electron beamlets on/off. The operation of the LSI was confirmed and 1/100 reduction electron optic system using the active matrix emitter array was fabricated. A 17×17 nc-Si emitter array was assembled with a 1:1 exposure test system and driven by commercially available display driver LSIs. The active matrix electron beam (EB) exposure was confirmed.

After years of optimistic projections and false starts, 2019 is finally the year that EUV will enter volume production. Mask shop investment in EUV-capable equipment, including writing, inspection, metrology, repair, review and cleaning tools as well as related infrastructure for storage, transportation, and pellicle support has been substantial. However, in both mask shops and wafer fabs, key questions remain unanswered even as high volume manufacturing (HVM) begins in the fab. We will highlight several of these questions that still need to be answered to develop comprehensive, end-to-end strategies for mask inspection, use, and qualification strategies. In particular, we will show how uncertainty over pellicle technology options and timing cascade into a series of questions related to reticle qualification flows throughout the lifetime of a mask. Additional uncertainty comes from the lack of data on reticle contamination mechanisms during use in high-power EUV exposure tools. Concerns over hydrocarbon deposition and reaction with intense EUV photons as well as with the out-of-band DUV present in the system, will require the development of careful monitoring and re-qualification plans. Reticle requalification cycles will be gated not just by the number of wafers exposed, but by the number of times a reticle is loaded and unloaded from the scanner and how long it sits in storage between cycles. We anticipate that a combination of wafer-based and reticle-based inspection will be required to fully ensure reticle quality, especially if a pellicle solution is adopted which does not allow 193nm based inspection. These tradeoffs and uncertainties will be discussed in the context of a full, mask blank to wafer fab reticle qualification strategy for EUV volume manufacturing.

Based on the record for reasonable throughput, 19x nm wavelength inspection is one of the strongest candidates available today for the initial EUV (Extreme Ultraviolet) mask inspection approach until high-throughput E-Beam or actinic inspection is ready. However, there are several key challenges with 19x nm optical inspection of EUV masks. In the previous study, it was demonstrated that a 19x nm inspection system was capable of detecting programmed 15nm edge defects and 7nm CD errors on the programmed defect mask (PDM) containing EUV device designs, and inspected at maximum sensitivity. However, in that study, the inspectability on the product mask was not considered. In this study, EUV product mask inspection with a 19x nm inspection system is demonstrated, with special attention paid to defect sensitivity and inspectability on the product mask. In our results, we discuss whether inspection conditions, such as focus, can be employed to create a trade-off between defect sensitivity and inspectability. In addition, we discuss how defect measurement definitions affect the programmed defect size and the printability on EUV AIMS.

TNO has built EBL2, an EUV exposure facility equipped with an in vacuo X-ray photoelectron spectroscopy setup (XPS) and an in-situ ellipsometer. EBL2 enables lifetime testing of EUV optics, photomasks, pellicles and related components under development in relevant EUV scanner and source conditions, which was previously not available to industry. This lifetime testing can help the industry to prepare for high volume production using EUV lithography by bringing forward information about material behavior which facilitates the development cycle. This paper describes an EUV photomask lifetime test performed at EBL2. The mask was exposed to different EUV doses under a controlled gas and temperature environment. To investigate how EUV light interacts with the mask, various analysis techniques were applied before and after EUV exposure. In-situ XPS was used to investigate elemental compositions of the mask surface. An ex-situ critical dimension scanning electron microscope (CD-SEM) and an atomic force microscope (AFM) were used to explore the impact of EUV light on critical dimensions (CD) and feature profiles. In addition, EUV reflectometry (EUVR) was used to investigate the change of reflectivity after EUV exposures. The exposure conditions are reported, as well as an analysis of the effects observed.

In next-generation EUV imaging for foundry N5 dimensions and beyond, inherent pitch- and orientation-dependent effects on wafer level will consume a significant part of the lithography budget using the current Ta-based mask. Mask absorber optimization can mitigate these so-called mask 3D effects [1-3]. Last year at the SPIE Photomask and EUVL conference [4,5], EUV mask absorber change is recognized by the community as key enabler of next-generation EUV lithography. Through rigorous lithographic simulations we have identified regions, based on the material optical properties and their gain in imaging performance compared to the reference Ta-based absorber [6]. In addition, we have established a mask absorber requirement test flow to validate the candidate material to the full mask supply chain. In this paper we discuss in more detail Te- and Ru- based alloys which cover these different improvement regions. Candidate materials are evaluated on film morphology, stability during combined hydrogen and EUV loading, and thermal and chemical durability. The EUV optical constants are measured by EUV reflectometry, and preliminary results of plasma etching are shown to enable patterning.

The EUV mask absorber structure is currently ~ 80nm thick TaN-based film, subtractively patterned through resist mask using dry reactive etch. A thin (2-3nm) Ru layer, below the absorber, protects the reflective Mo/Si multilayer, and acts as an etch stop. For future nodes, shadowing from an 80nm thick feature is considered prohibitive. Accordingly, more highly absorbing materials are being investigated, to allow a thinner absorber and reduced 3-D effects. For example, Ni, Pt and Pd are practical materials with EUV extinction coefficient more than double that of TaN, allowing for 25-40 nm absorber thickness. A challenge for Ni, Pt, or Pd--based absorbers is that reactive etch processes are unavailable. We discuss patterning of these materials by physical ion beam etch (IBE), the etch method of choice for these materials in magnetic or electrode applications. We demonstrate IBE etch rates up to ~80-200 nm/minute, implying process times of less than 20s. Via material and ion species optimization, we demonstrate etch selectivity to Ru up to ~ 1.8:1. Using SRIM simulations, we investigate ion damage through the underlying Ru layer, versus ion species and ion energy. Simulation predicts that any damage can be confined within a protective 2.5nm Ru layer, for ion energies of 200-400V. Depth of damage is reduced from ~8 nm to ~ 1.8 nm by reduction of the beam energy from 1200V to 200V. Based on the angular dependence of the IBE rates, we simulate IBE patterning of absorber structures, and demonstrate effective patterning down to 48nm mask half-pitch (~ 24nm wafer pitch for a 5nm node). Etched feature sidewall angles of 81-86o are demonstrated.

We investigate the current state of four functional specifications as they relate to EUV photomask blank flatness and the ways in which each functional specification limits, constrains, and controls aspects of image placement and focus error at the wafer following exposure. We explain the relationship between the functional specifications and the ultimate impact they have at wafer, by connecting the key performance indicators (KPIs) to their topographically related features at the mask. Sample mask data sets are then evaluated against the KPIs to demonstrate how such tolerances can open up the process window for certain photomask processing steps, while still achieving the overall lithography process specifications. This exploratory paper aims to offer an interpretation of what these topographic tolerances mean and ultimately help end users understand the potential implications of adopting such functional tolerances. A thorough understanding of such specifications will be necessary as the industry moves forward to future nodes, in order to successfully develop processes which adhere to the upstream tolerances necessary to create mask topographies which enable the mask to meet the high-performance requirements for successful wafer exposures.

Imprint lithography is an effective and well known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Given the risks associated with this introduction, generally a combination of both performance and cost advantage is preferred. In this paper both performance attributes and cost are discussed. NIL resolution and linewidth roughness do not have the limitations of conventional projection lithographic method. Furthermore, it is not subject to patterning restrictions that forced the industry towards one dimensional patterning. A cost example case of 20nm dense contacts is also presented. Because NIL utilized a single step patterning approach, process costs are substantially reduced relative to ArF immersion lithography. Overall, NIL currently realizes a 28% cost advantage for this case, but as mask life continues to improve, the cost advantages become much more significant.

Nanoimprint lithography (NIL) techniques are known to possess replication resolution below 5nm. A specific form of imprint lithography using jetted resist has been developed for manufacturing advanced CMOS memory. Canon’s NIL process involves field-by-field inkjet deposition of a low viscosity resist fluid followed by imprinting with nano-scale precision overlay. A mask with a relief structure is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is separated from the substrate leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In this work, improvements to the alignment system, together with the High Order Distortion Correction (HODC) system have enabled better distortion and overlay results on both test wafers and device wafers. The linear response of the HODC system was demonstrated for multiple high order terms and on test wafers, XMMO of 2.9nm and 3.2nm in x and y respectively was achieved. Additionally an SMO of 2.2nm and 2.4nm was achieved, with an opportunity to further improve results by applying wafer chucks with better flatness specifications.

In the last year, initial feasibility study results were published which showed that simulated fall-on particles and TEOS deposited pindot features could be removed with low-fluence femtosecond-pulsed laser repair processes with no detectable multi-layer damage as seen in AFM scans. At the time, actinic EUV inspection metrology was not available. In this work, this metrology is used with both process testing and removal of a more diverse range of different defect types both isolated (on multilayer and on absorber) and in patterns of various types and densities. In addition, follow-up work is shown to complete full factorial design of experiments tests for TEOS pindots in OMOG line and space patterns. These results are then parametrically analyzed and compared to simulation results and theoretical first-principles to better understand the mechanisms for defect removal from the EUV mask surface.

The currently increasing demand for photo-masks in the regime of the 14nm technology drives many initiatives towards capacity and throughput increase of existing production lines. Such improvements are facilitated by improved control mechanisms of the tools and processes used within a production line. While process control of long range parameters such as the average CD behavior is demanding yet conceptually well understood, other parameters such as the small scale CD properties are quite often elusive to process control. These properties often require a dedicated test mask to be processed in order to be validated. In this paper we introduce a systematic approach towards a product based monitoring of small scale CD behavior which uses a CD characteristic extracted from the defect inspection process. This characteristic represents the influence of CD relevant processes starting from 200 10^-6m up to 4000 10^-6m. Large variations in the scale and magnitude of the CD characteristic are induced by layout specific design variations. However, the shape of these distinct curves is remarkably similar, which enables their use for monitoring as well as controlling the mask processes on the above stated spatial scales. In this paper it is demonstrated, that a meaningful monitoring of the CD characteristic can be enabled through the use of machine learning methods. A classical monitoring scheme is typically based on measuring the deviation of each curve from the average behavior. However, the monitoring of a curve and deviations thereof often requires the evaluation of the overall shape of the curve. Thus we propose a monitoring concept which uses a support vector machine in order to learn the shapes of the CD characteristics. It is demonstrated that a statistical model of the CD characteristics can be trained and used in order to monitor single excursions (see Figure 1) as well as overall process changes.

As technical advances continue, the pattern size of semiconductor circuit has been shrunk. Defect control becomes tighter due to decrease in defect size that affects the image printed on the wafer. It is critical to the photomask which contained considerably shrunk circuit and ultra high density pattern for sub – 14 nm tech devices. Therefore particle source from all processes should be controlled extremely. Most of defects generated in mask fabrication processes have been mainly created during each unit process. In this paper, we introduce a study of airborne molecular contamination to Cr etching process. The impact of mask front-end handling system to defect generated in Cr etching process even in very lower concentration environment airborne molecular contamination. By the experiment results we will bring forward the possible defect generation mechanism. Based on this understanding, appropriate solution to mitigate defects caused by airborne molecular contamination to Cr etching process will be proposed.

In this study, we have made a breathable frame (outer sizes: 151mm x 119mm, frame width: 4mm, and frame height: 1.3mm) which has the mounting space for filters and the ventilation path inside of the frame. The breathable frame is composed of stacked layers of stainless thin plates with cutouts/openings. The breathable frame has a HEPA filter with filtration area of 600mm² inside. For a closed pellicle which consists of the breathable frame and p-Si pellicle membrane, time required for intake to 101kPa from 1Pa with keeping the deflection of p-Si pellicle membrane to 0.5mm was calculated at 165sec. It seems that the developed breathable frame has the useful ventilation performance. Furthermore, because special processing for ventilation, such as formation of a ventilation path is not required on the pellicle membrane, it is expected that the closed pellicle can be made easily by combining the existing pellicle membrane with the breathable frame.

RI Research Instrument’s EUV pellicle transmission qualification tool EUV-PTT uses "effective inband EUV measurement" which is spectrally filtering emission of the EUV-Lamp to 2% bandwidth at 13.5 nm for measuring "as seen by the scanner". Images of about 20x20 mm² are recorded in less than 5 seconds. A full pellicle characterization with < 60 images taken is accomplished in less than one hour. The first prototype of the EUV-PTT is in production quality control since nearly one year at our customer and achieving targeted quality in measurement and cleanliness and meets uptime specifications. Amongst additional aspects to be addressed in quality control is the reflection from the pellicle, which - in worst case - may impair the printing performance in the scanner. Hence, recently, we have performed concept studies on applying the PTT technique to carbon nano tube pellicles and on measuring the reflectance of low reflectance samples are reported. The latter is heavily demanding as reflectances in the range of 0.02 % were measured with sensitivities and reproducibilities in the range of 0.002 %.

In 14nm process critical layer, the weak pattern due to complex pattern designs will be revised aggressively by (OPC) Optical Proximity Correction. Therefore, the optical properties of these patterns will be extremely unstable. (Ex. High MEEF or Low contrast) In this circumstance, the mask process variation will impact the distribution of optical intensity for weak patterns quite considerably. In order to reduce the impact of the mask process variation, we add MPC (Mask process proximity correction) technique. Revising the mask process of ideal OPC masks again can make the result of masks meet our expectations better. In the paper, we show the comparison between the weak pattern of high MEEF with MPC and Non-MPC. We not only compare the optical behavior with the SEM Contour but also compare the variation of the real wafer process window. By means of the method in this paper, using MPC technique can definitely reduce the impact of the mask process variation and improve lithographic performance for weak pattern.

The mask-to-mask writing error contribution as part of the on-wafer intra-field overlay performance has been extensively studied over the past few years. An excellent correlation (R² > 0.96) was found between the off-line registration measurements by the PROVE tool and the on-wafer intra-field overlay results. The residual mismatch between the offline registration measurements and the on-wafer intra-field overlay was around 0.58-nm. This value is approximately 30% of the dedicated chuck overlay performance of the scanner that was used. A careful analysis was performed to understand and quantify the two dominant underlying contributors that are responsible for the 0.58-nm mismatch. The first contributor could be attributed to the reproducibility of the reticle alignment of the scanner (~0.43-nm after 10 wafers averaging). The second contributor was assigned to the sampling difference between the PROVE registration measurement and that of the alignment sensor inside the scanner (~0.39-nm). The sampling difference is a direct result of the relatively large metrology feature (alignment mark diffraction grating) in combination with older generation e-beam mask writing tools that were used in the experiments. Local grating placement variations are averaged out when the scanner alignment sensor is used for an overlay measurement. This is due to the large spot size and the scanning principle to obtain a position. This is fundamentally different for a mask registration tool since it has been designed to perform dedicated measurements on single features (globally or in-die) across the entire mask. Previous investigations used only two sampling points for each individual alignment mark diffraction grating in order to keep the total number of measurements and time under control. It is expected that the sampling difference will significantly decrease if state-of-the-art mask e-beam writers are used and/or if the number of sampling points as measured by the PROVE will be increased. It might be obvious that the ability to perform dense off-line local registration measurements has large value to reveal local mask writing errors. The new local registration map (LRM) mode of PROVE can be used to average out local reticle writing errors enabling a more accurate placement determination of large metrology features like reticle and/or wafer alignment marks. The application of LRM can be used to further improve the accuracy between the scanner and the PROVE mask registration tool if required. So far, all published correlation studies between off-line mask registration measurements and on-wafer overlay measurements were based on TIS (Transmission Image Sensor) reticle alignment marks. In this paper, we have applied LRM to improve the placement accuracy of more advanced PARIS (Parallel ILIAS) reticle alignment marks. A comparison with on-wafer measurements is made. In addition, the placement accuracy of a wafer alignment mark is considered as well. The impact of a wafer alignment mark placement error due to reticle writing errors on the intra-field overlay is experimentally determined and discussed. This includes the effect of an applied intra-field scanner (reticle alignment) correction on the wafer alignment mark placement.

Nanoimprint lithography (NIL) is promising technology for next generation lithography for the fabrication of semiconductor devices. The advantages of NIL are simpler process, less design rule restriction, which lead to lower cost-of-ownership, compared with conventional optical lithography. NIL is one to one lithography and contact transfer technique using template. Therefore template quality variations impact on wafer performance directly. To introduce NIL technology to high volume manufacturing (HVM) of semiconductor devices, improvement of template quality is very important. In the situation of pattern size shrinking, it is necessary to improve CD uniformity and defectivity to achieve the target of HVM. So that high accuracy QA (Quality Assurance) tools are required to qualify CD uniformity and defectivity which are key metrics on high-end template development. In this paper, we show the current status of template development for sub15nm NIL. For the template fabrication, double patterning technologies were applied to extend pattern resolution limit. Template replication was also implemented by template replication system Canon FPA1100-NR2. Finally we will show QA examples for high accuracy template by using key metrics such as CD uniformity, defectivity and Cross-sectional profile.