The VHSIC program is, by now, quite well known to many of you. I would like, however, to take a few minutes to review both the origins and the current status of the VHSIC program and particularly those areas which relate to high resolution, high throughput lithography for submicron silicon integrated circuits.

This paper presents submicron resolution test data from a wafer-stepper with a prototype Zeiss I-line lens (436 nanometers). The system demonstrates high-quality 0.5-micron lines and spaces on flat surfaces, and easily obtains 0.75-micron lines and spaces on a variety of surfaces. SEM data on step coverage and depth of focus are presented; process dependencies and special features of the 436-manometer light interaction with photoresist are highlighted. Theoretical expectations for resolution and depth of focus are experimentally shown to be valid, and extrapolations for future lenses promise even deeper penetration into the submicron region.

For photolithography to become a technique enabling the submicron field to be reached, research work on resist exposure tools and principles is not in itself sufficient. It is also necessary to try to use all the possibilities offered by technological procedures such as coating and dry etching to the full. It is for this reason that we have been led to develop recent microlithography techniques using plasma etching to condition the substrate flatness as well as the etching profiles, and similarly to transfer fine geometries with accurate dimensional control. In this paper, we will present sloping wall etching, planarization and spacer production techniques.

A plasma etching process for polycrystalline silicon with an etch ratio of 100:1 to thermal oxide has been developed. Sulfur hexafluoride containing 9% chlorine has been excited, at a rf power of 150 watts and at a total pressure of .100 Torr (13.3 Pa), to etch polysilicon. A decrease in the etch ratio of silicon to oxide with increasing overetch time has been observed. The etch profiles were nearly vertical and the vertical to lateral etch rate ratio was nearly 8:1. A model consistent with the experimental observations has been proposed. The process has been used successfully to clear polysilicon over steps of a height of approximately 0.75 pm without disturbing the structural integrity. Owing to its high selectivity to oxide and good linewidth control, the process can be used for fabricating VLSI circuits with thinner gate oxides.

Patterning of 1.0-2.0 μm features in polysilicon, TaSi₂,/polysilicon (polycide) and aluminum films requires highly directional and selective etching techniques. Chlorine based reactive ion etching in a hexagonal cathode reactor can be used to achieve these profile control goals. The major factors affecting the degree of etch directionality in this system are the dc self bias voltage and etch rate. For example, anisotropic etching of Al can be performed in BC1₃/C1₂ plasmas at a dc self bias of -200 V. As this voltage is lowered, the lateral etch rate increases with respect to the vertical etch rate giving a nearly isotropic line profile at -100 V. At a given dc self bias voltage, anisotropic etching is favored by low etch rates. A similar voltage and etch rate dependence is found for etching of polycide in BC13/C12 plasmas. Polysilicon etching in C1₂/SF₆ plasmas displays the etch rate dependence without the voltage dependence. In each process selectivity for SiO₂ and photoresist degrades as the dc self bias potential becomes more negative.

Yield data presented both for meander tracks and for contact chains show that the latter are considerably more vulnerable to defects involved in wafer processing, especially at the smaller feature sizes. A yield model, which is extended to cater for this difference, is applied to aspects of the scaling of integrated circuits.

A diffraction grating alignment system has been demonstrated on a GCA stepper. Registration of better than 0.2 microns, 3 sigma has been achieved on NMOS production wafers.

Very high registration accuracy is required for 5:1 wafer steppers used in V-LSI production. The image quality of an alignment mark is affected by illumination wavelength, photoresist thickness, light absorption in the photoresist, and by the characteristics of the alignment mark itself. Reflection Modeling and image profile analysis are applied to evaluate the influence of the alignment geometry and image quality on the ability to align the wafer. As a result of this study, ideal image quality is observed by optimization of the step height, and the influence of background noise is studied on rough aluminum surfaces. Degradation of the image profile and edge contrast are observed on rough aluminum surfaces.

In recent years, much attention has been focused on the performance of automatic alignment systems used in the projection printing of semiconductor devices. This is as a result of the progressive tightening of overlay specifications for device processing in response to the ever present pressure to increase device packing density(1-4). This paper reports studies on the performance of the linear array camera automatic fine alignment system on the Model 500 1:1 projection system. The work was carried out on wafers fabricated using an NMOS process sequence, and took the form of an applications study directed at answering the question "What is the overlay performance of the Model 500 projection printer when used in a device production situation?"

The theory and practical concerns of multi-layer techniques using an anti-reflective polymer coating will be discussed. Anti Reflective Coating (ARC, Brewer Science, Inc.) was incorporated into the metal lithography process for a 1.2 micron gate CMOS prototype production line. Previously, reflections from substrate topography had caused a loss in linewidth control. These reflections were minimized by the ARC, which also restored process latitude. For the process described, ARC coating uniformity was ± nm, adhesion was good, and step coverage was seen to be adequate to 0.8 micron high verticle wall steps.

Step and repeat projection aligners have evolved as the major lithographic system in the development of VLSI technology. High numerical aperture lenses get the resolution down to 1.0um or smaller, while the fully automatic field-by-field alignments provide the potential for achieving overlay accuracy of a small fraction of a micron. This paper will discuss the various options available to the users of Optimetrix 8010 (10 to 1 system) wafer steppers to get the best overlay registration. The effect of autoalignment iterations and autoalignment limits will be discussed against throughput and overlay registration on various substrates. A new alignment mark was used to achieve better alignment accuracy and automatic dia camera feature on the system was also evaluated. As a device becomes more complex and occupies a larger area, intradie pattern distortions (hence system-system) may significantly contribute to overlay error. This intradie pattern distortion may be caused by temperature fluctuations and distortion inherent in the design of the lenses. Both of these factors were evaluated and the intradie overlay errors are compared to interdie overlay errors. These interdie and intradie overlay errors determine the total stepper error which must be incorporated in the design rules.

The sources of errors arising in the implementation of a Censor SRA100 wafer stepper in a CMOS process are analysed with reference to a specially designed standard alignment mark. Results confirm that the registration performance of the machine is in the range 0.2 to 0.4μm and indicate critical areas for attention to attain a registration consistently below 0.20μm. The paper is divided into two main sections: metrology and process experience.

Automatic alignment has been offered by most manufacturers of alignment tools in recent years, and is regarded as essential in acheiving the overlay accuracy required to produce the current generation of fine-line integrated circuits. However, problems associated with the automatic alignment technologies themselves can offset the gains achieved and can, in worst case, actually degrade overall registration performance. Two important problems which must be overcome are: Autoalignment offsets which can cause alignment accuracy to deviate by more than a micron, even though precision is quarter micron or better. 2. Process-dependent variations- causing changes in the topographical and optical characteristics of the alignment keys which can change or degrade the signal produced by the key.

The use of Fresnel Zone Plates as alignment targets for both x-rayl and optical2 lithography has generated a need for understanding their focusing properties after they have been exposed to semiconductor processing procedures. Semiconductor processing can result in variation of radial dimensions, variation of contrast, and in variation of topography, all of which can impact upon the focusing properties. In this paper we report our measurements and calculations of the axial and radial intensity distribution of monochromatic light on zone plates used for optical alignment purposes. Measurements of the axial and radial intensity distribution were made with a conventional metallurgical microscope with the white-light source replaced with a HeNe laser. Calculations were an approximate solution of the Fresnel-Kirchoff Integral and an exact solution of Maxwell's Equations. 2 For Fresnel Zone Plates exhibiting r2 symmetry where the radii are given by rm = mAfl, m = 1,2,3.....2N, where N= the number of periods and fl = the primary focus, theory indicates that equal intensities be observed at ± fl, ± f3, ± f5,.....where f3, f5, are the odd submultiple foci. Even submultiples are zero. The linewidth decreases as the submultiplier increases. For a Fresnel Zone Plate with f1 = 200 microns, N=4 and X = 632.8nm, we observe equal intensities at ± f1 and ± f3 and reduced intensity at ± f5. The linewidth at fl is about a factor of ten larger than at f3. With alteration of the r2 symmetry, even-valued submultiple foci appear first, and with continued variation a total redistribution of the light along the z-axis is observed. Variation of the reflectivity of the zones, variation of the thin-film thicknesses and variation of the optical path difference bewteen zones can result in large intensity variations at the primary focus. The superposition of photoresist with neither conformal nor planarizing topography can result in loss of intensity. However, if the photoresist thickness is properly chosen this loss is not significant. Several processing examples are given.

Pellicles are thin transparent membranes of high optical quality that are placed on one or both sides of an IC circuit mask to protect the mask and to prevent any particulate defect falling onto the mask from affecting the printed image [1]. Pellicles have been successfully utilized in production with 1:1 scanning systems and have given measureable improvements in yield [2].

The use of pellicles as protection for photo masks and reticles to increase die yield, has become increasingly accepted in the semiconductor industry. To meet the changing needs of this industry with the more rigorous requirements of ever-decreasing geometries and lower wavelengths of exposure, a new type of pellicle had to be designed. This pellicle had to meet or exceed all the physical and mechanical requirements of the state-of-the-art pellicles, while combining a superior transmission that permits its use not only in the near-UV, but also in the mid-UV and deep-UV regions and for both steppers and projection aligners.

An automated He-Ne laser spectrometer is used to explore fundamental issues associated with non-destructive IC process monitoring on diffraction from drop-in test sites. The system is also used to explore how diffraction alignment signals are affected by incidence angle variations and resist coating. The apparatus consists of an x-ray spectrometer stage which has been retrofit with a He-Ne laser system. The system is automated through the use of an IBM-PC with stepping motor controllers and an auto-ranging current to voltage converter. The diffraction from 3.0µm period features on a specially fabricated wafer consist-ing entirely of drop-in test sites is characterized and correlated with other optical and SEM measurements. Site-to-site correlations across the wafer in various directions show a very significant "bull's eye" effect especially beyond a 3 cm radius. A similar sensitivity is not seen in either image-shearing or line-edge-scanning optical measure-ments. Theoretically, a physical optics model for the diffraction from the structure is shown to be too approximate to predict the measured site-to-site diffraction signals. To explore issues associated with diffraction based alignment, such as might occur with zone plate alignment signals, the first order diffraction is studied as a function of incidence angle and resist coating thickness. The incidence angle did not show rapid variations which might be expected while resist thickness changes gave very significant signal level fluctuations.

The feasibility for using a combination of ultraviolet light and ozone - UV/Ozone Cleaning - for organics removal and photoresist residue cleaning from silicon semiconductor wafers was investigated. The process generates a highly oxidative atmosphere that is specific for removing trace organic residues. Product of the reactions are carbon dioxide and water. In most cases, stable inorganic materials such as oxide coatings remain unaffected. UV/Ozone exposure of silicon causes formation of a thin layer of silicon oxide that tends to retard further oxidation of the silicon. Based on the expected photochemistry o," this process, specific enhancements to accelerate the cleaning rates were tested. The enhancements involved the use of both gas phase and liquio phase additives, and comparative rates of removal were determined. The technique was tested on several photoresists, potential organic residues, and common solvent systems. The photoresists studies were primarily positive resists and were tested at several levels of ion implantation. The results of the testing suggests that the highest potential applications of UV/Ozone Cleaning in the processing of semiconductor wafers include: a) Removal of solvent residues and process contaminants. b) A pre-process step to insure cleanliness by removal of residual organic or airborne organic contaminants. c) As a post-process step to insure cleanliness or to remove trace organics.

A new method is described which permits fully automated, high-speed measurement and compensation of the residual alignment and focusing offsets in advanced wafer step-and-repeat aligners which, despite being very small (0.1 micron range), cannot be tolerated in high performance lithography. A special reticle is projected onto a special measuring field to determine the exact position of the image in the exposure light. This position is used to calculate the alignment and focusing offsets between the aligned image and the actual image. The autocalibration procedure described represents a considerable advance over the present state-of-the-art, cutting down machine set-up times from hours to 90 seconds. The residual offsets are reduced to ± 0.05 μm (3 d ) for alignment and ± 0.15 μm (3 6 ) for focusing.

Measuring the overlay registration of wafer steppers is often a tedious, time-consuming task that is subject to inaccuracy and operator subjectivity. Electrical measurements of overlay can be quite accurate, but they require special equipment that is often not found in a wafer fab area, and there can be an undesirable delay before the results of the tests can be obtained. This paper describes a technique that can be used to quickly and automatically measure the overlay registration of multiple steppers on a wafer fab line. By analysis of the test results, it is possible to identify the specific sources of some of the overlay errors. Variations in the stage stepping patterns from one machine to another can be reduced by using the results of the tests to cause the machines to emulate the stepping pattern of a desired standard.

Lithographers have responded to the industry's challenge to produce precise resist patterns as circuit features shrink to one micron. These precise resist patterns must with-stand higher powered, dry processes without loss of image integrity. The first generation of positive resists do not withstand high temperature processes, and the second generation of "high temperature" positive resists are inadequate to withstand the most difficult process environments such as plasma etching of aluminum alloyed with copper. This paper describes a new process using ultraviolet light and controlled temperature operation to stabilize first and second generation positive resists at production throughputs while eliminating the need for hardbakes. Reduced erosion rates in metal etch have been obtained vs the plasma stabilization and hardbaking technique. The process, called UV/BAKE, increases the wafer temperature above the normal resist flow temperature during the exposure. The high temperatures, which greatly accelerate the stabilization process, can be accommodated without loss of image integrity due to an increasing degree of crosslinking brought about by the exposure to UV. Typically positive resists can be fully stabilized by a 42 second exposure to intense UV while increasing the wafer temperature from 1000 C to 200 C. SEM analysis verifies the effectiveness of this stabilization process to enable several common positive photoresists to withstand high temperature and planar plasma etching of aluminum. This paper also describes a modified UV/BAKE L" process for stabilizing two-layer resist structures.

Resist image critical dimension control is a major concern in photolithographic processing. Many processing factors have first and second order effects making critical dimension control very difficult to maintain within reasonable tolerances. As the industry continually drives resist images to the sub micron geometries, it is no longer acceptable to have critical dimension variations across the wafer exceeding 10% of the nominal value if the process critical dimensions are to be maintained. Many of us are now facing the fact that process windows are collapsing to + 0.1 microns on critically defined levels. One of the first order factors in controlling and minimizing these critical dimension variations is the developing step. Currently, our production line at Inmos has two types of puddle developer tracks and a developer track with the vapor jet nozzle. Extensive evaluation and comparisons of these three systemsshow that superior control of both wafer to wafer and across wafer critical dimension uniformity is achieved with the system equipped with the vapor jet nozzle. Data shows that line width or space control of + .04 microns may be achieved across the wafer and wafer to wafer on flat (no topology) wafers with the vapor jet nozzle. Critical dimension control of + .06 microns is demonstrated on wafers with topology. These control limits are based on critical dimension measurements taken on material processed under standard production conditions.

A new Laser Pattern Generator (LPG) designed for reticle production was recently introduced by THE Semiconductor Equipment Corporation. The system uses HeCd laser radiation with a wavelength of 441.6 nm to expose commercial photoresist (e.g. AZ 1350J or AZ 1470). A writing rate of 160 Mpx/sec is achieved by parallel operation of sixteen (16) independently modulated channels. The binary light intensity distribution is controlled in each channel by acousto-optic modulation. The sixteen (16) independent chan-nels are brought to a common crossover and scanned simultaneously using a single acousto-optic deflector. Pattern data must be expanded into a pixel format in two steps due to the inherent writing speed of the LPG. Prior to run time, geometrical data is trans-lated from Electromask or Mann format into a compact vector format using an off-line preprocessing unit. The vector data is stored on a 300 Mbyte portable disk pack which has a nominal data transfer rate of 9.67 Mbits/sec. During run time, vector data is read from the disk and expanded in the real time processing unit to supply pixel data to the optical modulation system. The placement of data in the correct position is controlled by a laser interferometry system and a control computer. The LPG system throughput of 160 Mpx/ sec permits the writing of 100 mm x 100 mm rejicles with information equivalent to 10' optical pattern generator flashes in less than 30 minutes, independent of pat-tern complexity. Although the specified minimum geometry is 2.5 pm, patterns with 1 pm features have been resolved. The address resolution is 0.25 μm, and the individual beam spot size is 0.5 μm (FWHM). Examples of printed patterns are included.

Optical properties of thin Cr/Crx0y films sputtered on glass for photomask making are investigated using Auger spectroscopy, ellipsometry and ref lectometry techniques. The films selected for the study vary from oxygen very rich to very poor. The complex indices of refraction are derived from the ellipsometry data using metal film calculation. The reflectance is then calculated to compare with that directly measured. These comparisons are important in understanding the film properties and their application in microlithography. The optical properties are found to be closely related to the oxygen concentration and its profile in the film. Optical intensity profiles in the photoresist are calculated for various photoresist/Cr/Crx0 systems, yielding optimal conditions for min4izing resist line-width variations. An experiment is also carried out to illustrate the main points predicted by the theory.

The imaging characteristics of masks which have arbitrary phase shifts between adjacent regions has been investigated. The process simulation program SAMPLE was extended to compute images of masks with an arbitrary number of regions of varying amplitude and phase transmission. In order to do this, the code was modified to calculate the imaginary, in addition to the real, part of the transmission cross-coefficient and perform complex multiplications within the image intensity summation. The disadvantage of phase shift masks lies in the high printability of defects. Phase shifts of 180° cause defects twice as small to print. This printability is phase shift dependent, and may be considerably reduced with smaller phase shifts. A second disadvantage is that phase shifts occurring in the middle of large clear areas produce such a deep dip in the image intensity that these clear field transitions are impractical. The advantage of phase shift masks lies in reducing proximity effects between adjacent features. The best measure of this reduction is the improvement in image con-trast for periodic arrays of lines. A significant improvement can be obtained, especially at low sigma. This improved contrast enables a smaller linewidth to be used. At a sigma of 0.3 the size of periodic features may be reduced from 1.2 μm to 0.5 μm, still maintaining a contrast of 0.85. Not only is the contrast improved, but its sensitivity to defocus is actually reduced, thereby increasing the useful depth of focus. Phase shifts less than 180° give similar results although the improvement decreases rapidly for phase shifts less than 120°. The image of isolated features may be improved 30 percent by using unprintable phase shifted proximity features. By proper defect control and elimination of clear field transitions, very significant improvements in aerial image quality are possible with phase masks.

Wafer steppers require contaminant-free reticles to assure high yield. This paper describes a new particle detection technique. A linearly polarized He-Ne laser beam scans obliquely across the reticle surface and only scattering light produced by the particles is detected by the detectors, which consist of analyzers, collection lenses, slits, and PMTs (photomultipliers). On the other hand, scattering light produced by the pattern edges on the reticle is cut off by the analyzers. Using this technique, particles as small as 2 1im on the surface of pellicle-installed reticles can be detected.

A reticle contamination monitor having enough sensitivity for a 5:1 stepper has been developed. By scanning a laser spot in a raster mode and monitoring the light scattered by particles, this apparatus can detect spherical beads of 2 μm or larger diameter and various kinds of particles of 5pm or larger size. In order to detect small particles without the disturbance due to the light intensely scattered by reticle patterns, and to distinguish particle light signals from pattern light signals, the monitor has plural detectors arranged to receive scattered light rays that proceed in different directions. It takes two minutes to inspect both surfaces of a reticle of which inspection area is 100mm X 100mm. An automatic reticle transfer mechanism with this monitor is built into a stepper, so that a reticle is moved from a reticle case to both the inspection box and the exposure station without being contaminated. Periodic inspection with this apparatus prevents the deterioration in yield caused by reticle contamination. And a new type of reticle cleaner equipped with this contamination monitor has been developed to make it easy to clean a reticle.

Fabrication of VLSI devices with complex designs and one micron geometries presents a major challenge in the area of quality assurance. The original CAD design can be used as the reference for inspection, if a mechanism is provided for compensating for the effects of the process on the design. Using this approach, Contrex has developed a system for wafer inspection that accurately predicts the shape of a pattern in photoresist, and is able to detect defects as small as 0.3 microns.

This is the introduction of new technology developed specifically for the inprocess pattern inspection and measurement of very large scale integrated (VLSI) wafers. There is a current need for significant improvements in pattern inspection instrumentation in order to tighten process control and achieve more competitive yields and therefore die costs. For the tedious and detailed task of pattern inspection and measurement, automation is the indicated solution. The future of computerized manufacturing requires, most fundamentally, the automation of the instrumentation and control function. In this paper, a system, designated the KLA 2020 Wafer Inspector, is described which incorporates the basic functions required to measure variations in the patterning process: linear and area dimensional measurements, registration error measurement, comparison for defects down to submicron in size. It is capable of inspecting in-process wafers in order to gain the most immediate process feedback. The speed with which it does each of these tests, less than a second, allows significant increases in sample size and therefore statistical control. It is this technology which will make computer-controlled photo processing possible.

A completely automated vision system for inspection of in-process and fully patterned integrated circuits (ICs) has been demonstrated. Applied to the inspection of a Darlington IC, the EYESEE system is shown to effectively replace an operator in performing inspections such as those called for in MIL-STD-883B, method 2010. EYESEE has been extended to inspection of certain LSI and VLSI devices for characterization and measurement of line widths and critical dimensions, mask and reticle registration accuracy, and gross and fine defects. EYESEE general video image processing technology has reached the point where technical feasibility has been established for automating many semiconductor inspection tasks. A comprehensive review of other relevant computer vision techniques used within the semiconductor manufacturing industry is presented.