Analysis of current transients in SRAM memories for single event upset detection

G. Torrens; S. Bota; J. Verd; B. Alorda; J. Merino; J. Segura

doi:10.1117/12.821476

28 May 2009 Analysis of current transients in SRAM memories for single event upset detection

G. Torrens, S. Bota, J. Verd, B. Alorda, J. Merino, J. Segura

Proceedings Volume 7363, VLSI Circuits and Systems IV; 73630Z (2009) https://doi.org/10.1117/12.821476
Event: SPIE Europe Microtechnologies for the New Millennium, 2009, Dresden, Germany

Abstract

Soft errors resulting from the impact of charged particles are emerging as a major issue in the design of reliable circuits at deep sub-micron dimensions even at ground level. To face this challenge, a designer must dispose of a variety of mitigation schemes adapted to their specific design constraints. Built In Current Sensors have been proposed as a detection scheme for single event upsets in SRAM. In this paper, Power-Bus current transients in SRAM memories for Single Event Upset Detection have been analyzed in a 65nm CMOS technology. The different types of current roles which are applied during the simulation is discussed. The results show the important contribution of leakage currents in the response of the memory cell to an external event.

Citation Download Citation

G. Torrens, S. Bota, J. Verd, B. Alorda, J. Merino, and J. Segura "Analysis of current transients in SRAM memories for single event upset detection", Proc. SPIE 7363, VLSI Circuits and Systems IV, 73630Z (28 May 2009); https://doi.org/10.1117/12.821476

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