An efficient optimized JPEG 2000 tier-1 coder hardware implementation

Paul R Schumacher

doi:10.1117/12.503084

23 June 2003 An efficient optimized JPEG 2000 tier-1 coder hardware implementation

Paul R Schumacher

Proceedings Volume 5150, Visual Communications and Image Processing 2003; (2003) https://doi.org/10.1117/12.503084
Event: Visual Communications and Image Processing 2003, 2003, Lugano, Switzerland

Abstract

It is a well-known fact that the major bottleneck of a JPEG2000 encoder is the bit/context modeling and arithmetic coding tasks (also known as the tier-1 coding portion of EBCOT). Whereas the technique of using mutiple coding passes on multiple bit-planes follows a near-optimal path on the rate-distortion curve and helps create an elegant embedded codestream, this tier-1 coding requies a large amount of computation for each block of data as well as significant memory resources and memory accesses. Luckily, the JPEG2000 standard allows us to perform a number of the tier-1 coding tasks in parallel. If this parallelization is exploited and if smart data organization techniques are used, then the throughput of a JPEG2000 system can be dramatically improved. This paper discusses an efficient, optimized hardware implementation of a tier-1 coder that exploits these available parallelisms. This paper also describes implementation on Xilinx FPGA platforms. The proposed technique described in this paper is approximately 50% faster than the best technique described in the literature.

Citation Download Citation

Paul R Schumacher "An efficient optimized JPEG 2000 tier-1 coder hardware implementation", Proc. SPIE 5150, Visual Communications and Image Processing 2003, (23 June 2003); https://doi.org/10.1117/12.503084

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