Very large scale integration (VLSI) architecture for motion estimation and vector quantization

Shih-Yu Huang; Kuen-Rong Hsieh; Jia-Shung Wang

doi:10.1117/12.185930

16 September 1994 Very large scale integration (VLSI) architecture for motion estimation and vector quantization

Shih-Yu Huang, Kuen-Rong Hsieh, Jia-Shung Wang

Proceedings Volume 2308, Visual Communications and Image Processing '94; (1994) https://doi.org/10.1117/12.185930
Event: Visual Communications and Image Processing '94, 1994, Chicago, IL, United States

Abstract

A hardware design, called the ME/MRVQ, which combines the functions of motion estimation (ME) and mean/residual vector quantization (MRVQ) is proposed to improve the coding quality of MPEG in this paper. In the ordinary MPEG design, the ME hardware is idle while coding I-pictures. In general, the process of motion estimation is quite similar to the work of vector quantization coding. They all try to search a best representative from a set of exemplars for every input block. In our design, we perform an extra VQ coding in intraframe compression utilizing the idle hardware for motion estimation. A new intraframe coding scheme, called the cascading MRVQ-DCT, is proposed for incorporating this hardware design. The cascading MRVQ-DCT performs a VQ coding before executing DCT, quantization and VLC coding. It has the advantages of coding the shade vectors by VQ and coding the edge vectors by DCT. Thus, the blocking effects in DCT coder under low bit rate is cured. The coding efficiency of the cascading MRVQ-DCT scheme is investigated by software simulations. It is shown that the rate-distortion performance is uniformly improved.

Citation Download Citation

Shih-Yu Huang, Kuen-Rong Hsieh, and Jia-Shung Wang "Very large scale integration (VLSI) architecture for motion estimation and vector quantization", Proc. SPIE 2308, Visual Communications and Image Processing '94, (16 September 1994); https://doi.org/10.1117/12.185930

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