IC design of optimal four-bit absolute value detector based on CMOS process

Haihang Xia; Nianyi Xiang; Mingzhe Zhao

doi:10.1117/12.2627202

14 February 2022 IC design of optimal four-bit absolute value detector based on CMOS process

Haihang Xia, Nianyi Xiang, Mingzhe Zhao

Proceedings Volume 12161, 4th International Conference on Informatics Engineering & Information Science (ICIEIS2021); 1216116 (2022) https://doi.org/10.1117/12.2627202
Event: 4th International Conference on Informatics Engineering and Information Science, 2021, Tianjin, China

Abstract

Design and implement a high-performance absolute-value detector through the CMOS process, and realize the function of taking the absolute value of the input data and then comparing it, which can be applied in a variety of circuits, such as A/D conversion. The circuit structure is simple, which adopts the structure of the mirror adder and the multiplexer. This paper also looks for the critical path and uses logical effort theory to find the minimum delay. The next work is to adjust the gate size and determine the optimal size of the device and the optimal power supply voltage. Finally, this paper attempts to achieve the minimum energy consumption.

Citation Download Citation

Haihang Xia, Nianyi Xiang, and Mingzhe Zhao "IC design of optimal four-bit absolute value detector based on CMOS process", Proc. SPIE 12161, 4th International Conference on Informatics Engineering & Information Science (ICIEIS2021), 1216116 (14 February 2022); https://doi.org/10.1117/12.2627202

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