This PDF file contains the front matter associated with SPIE Proceedings Volume 9053 including the Title Page, Copyright information, Table of Contents, Introduction, and Conference Committee listing.

Quality and value of an IC product are functions of power, performance, area, cost and reliability. The forthcoming 2013 ITRS roadmap observes that while manufacturers continue to enable potential Moore’s Law scaling of layout densities, the “realizable” scaling in competitive products has for some years been significantly less. In this paper, we consider aspects of the question, “To what extent should this scaling gap be blamed on lithography?” Non-ideal scaling of layout densities has been attributed to (i) layout restrictions associated with multi-patterning technologies (SADP, LELE, LELELE), as well as (ii) various ground rule and layout style choices that stem from misalignment, reliability, variability, device architecture, and electrical performance vs. power constraints. Certain impacts seem obvious, e.g., loss of 2D flexibility and new line-end placement constraints with SADP, or algorithmically intractable layout stitching and mask coloring formulations with LELELE. However, these impacts may well be outweighed by weaknesses in design methodology and tooling. Arguably, the industry has entered a new era in which many new factors – (i) standard-cell library architecture, and layout guardbanding for automated place-and-route: (ii) performance model guardbanding and signoff analyses: (iii) physical design and manufacturing handoff algorithms spanning detailed placement and routing, stitching and RET; and (iv) reliability guardbanding – all contribute, hand in hand with lithography, to a newly-identified “design capability gap”. How specific aspects of process and design enablements limit the scaling of design quality is a fundamental question whose answer must guide future RandD investment at the design-manufacturing interface. terface.

Pattern matching tools have become increasingly common in physical design flows for verification and layout analysis. Recently developed topological-based pattern matching engines offer several advantages over conventional three-value logic implementations. In this paper the use of such topological engines is explored for measuring physical design regularity, driving improvements in overall regularity, and for implementing targeted enhancements for suboptimal layout configurations.

Design rule checks (DRC) are the industry workhorse for constraining design to ensure both physical and electrical manufacturability. Where DRCs fail to fully capture the concept of manufacturability, pattern-based approaches, such as DRC Plus, fill the gap using a library of patterns to capture and identify problematic 2D configurations. Today, both a DRC deck and a pattern matching deck may be found in advanced node process development kits. Major electronic design automation (EDA) vendors offer both DRC and pattern matching solutions for physical verification; in fact, both are frequently integrated into the same physical verification tool.

In physical verification, DRCs represent dimensional constraints relating directly to process limitations. On the other hand, patterns represent the 2D placement of surrounding geometries that can introduce systematic process effects. It is possible to combine both DRCs and patterns in a single topological pattern representation. A topological pattern has two separate components: a bitmap representing the placement and alignment of polygon edges, and a vector of dimensional constraints. The topological pattern is unique and unambiguous; there is no code to write, and no two different ways to represent the same physical structure. Furthermore, markers aligned to the pattern can be generated to designate specific layout optimizations for improving manufacturability.

In this paper, we describe how to do systematic physical verification with just topological patterns. Common mappings between traditional design rules and topological pattern rules are presented. We describe techniques that can be used during the development of a topological rule deck such as: taking constraints defined on one rule, and systematically projecting it onto other related rules; systematically separating a single rule into two or more rules, when the single rule is not sufficient to capture manufacturability constraints; creating test layout which represents the corners of what is allowed, or not allowed by a rule; improving manufacturability by systematically changing certain patterns; and quantifying how a design uses design rules. Performance of topological pattern search is demonstrated to be production full-chip capable.

Comprehensive and compact test patterns are crucial to the development of new semiconductor technology. In particular, the random nature of routing layers tends to create many hotspots, corresponding to patterns which are difficult to predict. Conventional group of test patterns consists of parametric typical patterns and real layout clips, which contain a lot of redundancy. The paper addresses a problem of generating comprehensive yet compact group of test patterns for random routing layers. A new method of pattern extraction and classification is proposed to solve the problem.

Pattern-based approaches to physical verification, such as DRC Plus, which use a library of patterns to identify problematic 2D configurations, have been proven to be effective in capturing the concept of manufacturability where traditional DRC fails. As the industry moves to advanced technology nodes, the manufacturing process window tightens and the number of patterns continues to rapidly increase. This increase in patterns brings about challenges in identifying, organizing, and carrying forward the learning of each pattern from test chip designs to first product and then to multiple product variants. This learning includes results from printability simulation, defect scans and physical failure analysis, which are important for accelerating yield ramp.

Using pattern classification technology and a relational database, GLOBALFOUNDRIES has constructed a pattern database (PDB) of more than one million potential yield detractor patterns. In PDB, 2D geometries are clustered based on similarity criteria, such as radius and edge tolerance. Each cluster is assigned a representative pattern and a unique identifier (ID). This ID is then used as a persistent reference for linking together information such as the failure mechanism of the patterns, the process condition where the pattern is likely to fail and the number of occurrences of the pattern in a design. Patterns and their associated information are used to populate DRC Plus pattern matching libraries for design-for-manufacturing (DFM) insertion into the design flow for auto-fixing and physical verification. Patterns are used in a production-ready yield learning methodology to identify and score critical hotspot patterns. Patterns are also used to select sites for process monitoring in the fab.

In this paper, we describe the design of PDB, the methodology for identifying and analyzing patterns across multiple design and technology cycles, and the use of PDB to accelerate manufacturing process learning. One such analysis tracks the life cycle of a pattern from the first time it appears as a potential yield detractor until it is either fixed in the manufacturing process or stops appearing in design due to DFM techniques such as DRC Plus. Another such analysis systematically aggregates the results of a pattern to highlight potential yield detractors for further manufacturing process improvement.

With the use of sub-wavelength photolithography, some layouts can have low printability and, accordingly, low yield due to the existence of bad patterns, even though they pass design rule checks. A reasonable approach is to select some of the candidate bad patterns as “forbidden”. With the use of sub-wavelength photolithography, some layouts can have low printability and, accordingly, low yield due to the existence of bad patterns, even though they pass design rule checks. A reasonable approach is to select some of the candidate bad patterns as forbidden". These are the ones with high yield-impact or low routability-impact, and these are to be prohibited in the design phase. The rest of the candidate bad patterns may be fixed in the post-route stage, in a best-effort manner. The process developers need to optimize the process to be friendly to the patterns of high routability-impact. Hence, an evaluation method is required early in the process, to assess the impact of forbidding layout patterns on routability. In this work, we propose Pattern-driven Design Rule Evaluation (Pattern-DRE), which can be used to evaluate the importance of patterns for the routability of the standard cells and, accordingly, select the set of bad patterns to forbid in the design. The framework can also be used to compare restrictive patterning technologies (e.g. LELE, SADP, SAQP, SAOP). Given a set of design rules and a set of forbidden patterns, Pattern-DRE generates a set of virtual standard cells, then it finds the possible routing options for each cell, without using any of the forbidden patterns. Finally, it reports the routability metrics. We present few studies that illustrate the use cases of the framework. The first study compares LELE to SADP, by using a set of forbidden patterns that are allowed by LELE but not by SADP. The second study investigates the area penalty as well as the SADP-compliance that we obtain if we increase the minimum gate-to-Local-Interconnect spacing design rule.

Due to the delay of EUVL, multiple patterning techniques have been used to extend the 193nm lithography to 22nm/14nm nodes, and possibly further. There are many studies on MPL layout decompositions at the mask synthesis stage to resolve the coloring conflicts, minimize the stitches, balance the mask density, or even mitigate the undesirable overlay effects. Meanwhile, there are studies showing that it is very important to consider the multiple patterning implications at earlier physical design stages so that the overall design and manufacturing closure can be reached. In this paper, we will show some recent results and propose a unified physical design methodology for standard cell compliance, pin access, routing, and placement to bridge the gap from mask/layout decomposition to physical design, while accommodating various requirements from double/triple patterning lithography in certain "correct by construction" manner.

This paper reviews the escalation in design constraints imposed on 2^nd level wiring by multiple patterning exposure techniques in the 10NM technology node (i.e. ~45nm wiring pitch) relative to the 14NM technology node (i.e. 64nm wiring pitch). Specifically, new challenges facing place-and-route tooling are outlined, solutions to overcome these challenges are reviewed, and a manufacturing ready implementation is demonstrated.

Logic manufacturers are looking towards a triple patterning solution for their 10nm node Metal1 layer, and possibly for Via0, and local interconnect layers. Given the NP-completeness for the 3-colorability problem, a challenge is how to go beyond a standard cell to efficiently decompose a layout at a block or chip level. Using decomposed or pre-colored standard cells does not always mean decomposable standard cell layouts can be placed next to each other. Posing constraints on how cells can be placed next to each other could cause area loss. A preferred way is to perform the decomposition at a block or chip level.

We have successfully developed a triple patterning decomposition methodology that can effectively decompose an entire layout block or a chip. Formulating a triple patterning decomposition problem into a graph 3-color problem, the system first builds a graph to represent the layout. It then tries to reduce and partition the graph without changing its 3-colorability property. To color the reduced graph, we adopt a hybrid approach with a fast heuristic for coloring and an exact coloring algorithm for backup and conflict verification.

Unlike an odd cycle in double patterning, a triple patterning coloring conflict can’t be represented in a single loop. Another challenge for triple patterning is then how to report errors that the user can effectively use to fix them. For this purpose, minimum fix guidance – minimum to fix a conflict, and maximal minimum fix guidance – maximal choices are presented.

In this paper, we present a benchmarking study of directed self-assembly (DSA) and self-aligned multiple patterning (SAMP) techniques for potential applications in manufacturing 10-nm (half-pitch) IC devices. Using the self-aligned quadruple patterning (SAQP) process as an example, we compare their process characteristics and complexity/costs, identify the integration challenges, and propose various patterning solutions for both BEOL and FEOL applications. Major differences in DSA and SAQP mask strategy, layout decomposition algorithm, and pattern-generation modeling are discussed, and critical requirements of overlay accuracy and CD control for implementing a DSA process in NAND wordline patterning are indentified. DSA technique is found to be a complementary solution for certain niche applications and we suggest that our industry should allocate more R and D resources to solve the 2-D SAMP layout decomposition challenges for logic BEOL patterning. We also propose an “out-of-the-box” idea of combining DSA and SADP process to significantly improve the 2-D design flexibility and develop a layout decomposition algorithm for this hybrid process

Self-Aligned Quadruple Patterning (SAQP) is one of the most leading techniques in 14 nm node and beyond. However, the construction of feasible layout configurations must follow stricter constraints than in LELELE triple patterning process. Some SAQP layout decomposition methods were recently proposed. However, due to strict constraints required for feasible SAQP layout, the decomposition strategy considering an arbitrary layout does not seem realistic. In this paper, we propose a new routing method for feasible SAQP layout requiring no decomposition. Our method performs detailed routing by correct-by-construction approach and offers compliant layout configuration without any pitch conflict.

As technology nodes continues shrinking, layout patterns become more sensitive to lithography processes, resulting in lithography hotspots that need to be identified and eliminated during physical verification. In this paper, we propose an accurate hotspot detection approach based on PCA (principle component analysis)-SVM (sup- port vector machine) classifier. Several techniques, including hierarchical data clustering, data balancing, and multi-level training, are provided to enhance performance of the proposed approach. Our approach is accurate and more efficient than conventional time-consuming lithography simulation; in the meanwhile, provides high flexibility to adapt to new lithography processes and rules.

Sub-20nm node designs are getting more sophisticated, and printability issues become more critical which need more advanced techniques to fix. It is mandatory for designers to run lithography checks before tapeout, and it is very challenging to fix all of the generated hotspots manually without introducing unintentional hotspots, or DPT violations. This paper presents a methodology for fixing hotspots on DPT layouts, using the same Model Based Hints (MBH) engine used for detecting hotspots. The fix is based on DRC and DPT constrained minimum movement of edges causing the hotspot, which guarantees that the fix does not violate any of the specified DRC or DPT constraints, nor does it need recoloring. The fix is extended along multilayers to fulfill the specified DRC and DPT constraints and guarantees circuit connectivity along the layers stack. This multilayers approach fixes hotspots that were impossible to fix previously. This methodology is demonstrated on industrial designs, where real hotspots were fixed and the fixing rate is reported.

Hot spot fixing (HSF) method has been used to fix many hot spots automatically. However, conventional HSF based on a biasing based modification is difficult to fix many hot spots under a low-k1 lithography condition. In this paper we proposed a new HSF, called configurable hotspot fixing system. The HSF has two major concepts. One is a new function to utilize vacant space around a hot spot by adding new patterns or extending line end edges around the hot spot. The other is to evaluate many candidates at a time generated by the new functions. We confirmed the proposed HSF improves 73% on the number of fixing hot spots and reduces total fixing time by 50% on a device layout equivalent to 28nm-node. The result shows the proposed HSF is effective for layouts under the low-k1 lithography condition.

As patterns shrink to physical limits, advanced Resolution Enhancement Technologies (RET) encounter increasing challenges to ensure a manufacturable Process Window (PW). Moreover, due to the wide variety of pattern constructs for logic device layers, lithographically weak patterns (spots) become a difficult obstacle despite Source and Mask co- Optimization (SMO) and advanced OPC being applied. In order to overcome these design related lithographically weak spots, designers need lithography based simulator feedback to develop robust design rules and RET/OPC engineers must co-optimize the overall imaging capability and corresponding design lithography target. To meet these needs, a new optimization method called SmartDRO (Design Rule Optimization) has been developed. SmartDRO utilizes SMO’s Continuous Transmission Mask (CTM) methodology and optimization algorithm including design target variables in the cost function. This optimizer finds the recommended lithography based target using the SMO engine. In this paper, we introduce a new optimization flow incorporating this SmartDRO capability to optimize the target layout within the cell to improve the manufacturable process window. With this new methodology, the most advanced L/S patterns such as metal (k1 = 0.28) and the most challenging contact patterns such as via (k1 = 0.33) are enabled and meet process window requirements.

With increasing chip sizes and shrinking device dimensions, on-chip semiconductor process variation can no longer be ignored in the design and signoff static timing analysis of integrated circuits. An important parameter affecting CMOS technologies is the gate length (Lgate) of a transistor. In modern technologies significant spatial intra-chip variability of transistor gate lengths which are systematic, as opposed to random, can lead to relatively large variations in circuit path delays. Spatial variations in Lgate affect circuit timing properties, which can lead to timing errors and performance loss. To maximize performance and process utilization in microprocessor designs, we have developed and validated a timing analysis methodology based on accurate silicon contour prediction from drawn layout and contour-based extraction of our designs. This allows for signoff timing without unnecessarily large margins, thereby reducing chip area and maximizing performance while ensuring chip functionality, improved process utilization and yield. In this paper we describe such a chip timing methodology, its validation and implementation in microprocessor design. We also report results of layout optimization based on new pattern matching technology.

DRAM chip space is mainly determined by the size of the memory cell array patterns which consist of periodic memory cell features and edges of the periodic array. Resolution Enhancement Techniques (RET) are used to optimize the periodic pattern process performance. Computational Lithography such as source mask optimization (SMO) to find the optimal off axis illumination and optical proximity correction (OPC) combined with model based SRAF placement are applied to print patterns on target. For 20nm Memory Cell optimization we see challenges that demand additional tool competence for layout optimization. The first challenge is a memory core pattern of brick-wall type with a k1 of 0.28, so it allows only two spectral beams to interfere. We will show how to analytically derive the only valid geometrically limited source. Another consequence of two-beam interference limitation is a ”super stable” core pattern, with the advantage of high depth of focus (DoF) but also low sensitivity to proximity corrections or changes of contact aspect ratio. This makes an array edge correction very difficult. The edge can be the most critical pattern since it forms the transition from the very stable regime of periodic patterns to non-periodic periphery, so it combines the most critical pitch and highest susceptibility to defocus. Above challenge makes the layout correction to a complex optimization task demanding a layout optimization that finds a solution with optimal process stability taking into account DoF, exposure dose latitude (EL), mask error enhancement factor (MEEF) and mask manufacturability constraints. This can only be achieved by simultaneously considering all criteria while placing and sizing SRAFs and main mask features. The second challenge is the use of a negative tone development (NTD) type resist, which has a strong resist effect and is difficult to characterize experimentally due to negative resist profile taper angles that perturb CD at bottom characterization by scanning electron microscope (SEM) measurements. High resist impact and difficult model data acquisition demand for a simulation model that hat is capable of extrapolating reliably beyond its calibration dataset. We use rigorous simulation models to provide that predictive performance. We have discussed the need of a rigorous mask optimization process for DRAM contact cell layout yielding mask layouts that are optimal in process performance, mask manufacturability and accuracy. In this paper, we have shown the step by step process from analytical illumination source derivation, a NTD and application tailored model calibration to layout optimization such as OPC and SRAF placement. Finally the work has been verified with simulation and experimental results on wafer.

A yield estimation model to evaluate the lithography distortion in a printed layout is presented. The yield model relates the probability of non-failure of a lithography hotspot with the manufacturing yield loss. We define a lithography hotspot as a pattern construct with excessive variation under lithography printing using lithography simulations. Thereby, we propose a pattern construct classifier to reduce the set of lithography simulations necessary to estimate the litho-degradation. The application of the yield model is demonstrated for different layout configurations showing that a certain degree of layout regularity improves the manufacturing yield and increases the number of good dies per wafer.

How to maintain the Moore’s Law scaling beyond the 193 immersion resolution limit is the key question semiconductor industry needs to answer in the near future. Process complexity will undoubtfully increase for 14nm node and beyond, which brings both challenges and opportunities for technology development. A vertically integrated design-technologymanufacturing co-optimization flow is desired to better address the complicated issues new process changes bring. In recent years smart mobile wireless devices have been the fastest growing consumer electronics market. Advanced mobile devices such as smartphones are complex systems with the overriding objective of providing the best userexperience value by harnessing all the technology innovations. Most critical system drivers are better system performance/power efficiency, cost effectiveness, and smaller form factors, which, in turns, drive the need of system design and solution with More-than-Moore innovations. Mobile system-on-chips (SoCs) has become the leading driver for semiconductor technology definition and manufacturing. Here we highlight how the co-optimization strategy influenced architecture, device/circuit, process technology and package, in the face of growing process cost/complexity and variability as well as design rule restrictions.

To date, majority of the papers presented in the conference focused on how to print smaller transistors that run faster. In a different market such as safety-focused automotive market, “smaller and faster” are replaced by “tougher and living longer”. In such a market, a chip has to endure a wide range of operating temperature from -40C to 150C, and is required to have an extremely low field failure rate over 10+ years. There is a wide range of design techniques that can be deployed to improve the quality of a chip. In this paper, we present some of these design techniques that are related to the physical aspects of standard cells.

An AC current induced electromigration (EM) on clock and logic signals becomes a significant problem even in the presence of reverse-recovery effect. Compared to power network, clock and logic signal interconnects are much narrower (mostly drawn up to the minimum width and space) and suffer from fast switching and large driving current from FinFETs. Thus, the high current density on those signal interconnects can cause a serious failure. In this paper, we analyse EM on signal interconnects in 16nm FinFET design, and characterize the impact of process variations, e.g., lithography and etch process, CMP (chemical-mechanical polishing) process, redundant via, etc. Then we optimize the signal lines with various design approaches to mitigate EM problem in 16nm design.

The density requirement expected for the 10nm node continues to increase the pressure on patterning. With the frontend of line adopting a regular layout (mostly unidirectional), most of the complexity needed for a functional chip ends up in the interconnect layer and Metal1. Assuming that Extreme Ultra Violet Lithography (EUVL) will not be ready for the early stage of 10nm production but only for high volume manufacturing, we have studied how ArF immersion lithography can be extended for Metal1 to sustain the development of the technology as well as the early production phase, while at the same time remaining compatible with an EUVL single patterning solution. We show how close interaction between design, process and computational lithography leads to a Metal1 triple patterning solution using Negative Tone Development (NTD), and how the same design solution can be supported by EUVL single patterning. Particular attention will be paid to line end printability performance, both tip to tip and tip to line, as we believe it is a key parameter to define the best compromise between lithography performance and design density.

This paper extends the state of the art by describing the practical material’s challenges, as well as approaches to minimize their impact in the manufacture of contact/via layers using a grapho-epitaxy directed self assembly (DSA) process. Three full designs have been analyzed from the point of view of layout constructs. A construct is an atomic and repetitive section of the layout which can be analyzed in isolation. Results indicate that DSA’s main benefit is its ability to be resilient to the shape of the guiding pattern across process window. The results suggest that directed self assembly can still be guaranteed even with high distortion of the guiding patterns when the guiding patterns have been designed properly for the target process. Focusing on a 14nm process based on 193i lithography, we present evidence of the need of DSA compliance methods and mask synthesis tools which consider pattern dependencies of adjacent structures a few microns away. Finally, an outlook as to the guidelines and challenges to DSA copolymer mixtures and process are discussed highlighting the benefits of mixtures of homo polymer and diblock copolymer to reduce the number of defects of arbitrarily placed hole configurations.

One of the most critical factors in achieving a positive return for a design is ensuring the design not only meets performance specifications, but also produces sufficient yield to meet the market demand. The goal of design for manufacturability (DFM) technology is to enable designers to address manufacturing requirements during the design process. While new cell-based, DP-aware, and net-aware fill technologies have emerged to provide the designer with automated fill engines that support these new fill requirements, design changes that arrive late in the tapeout process (as engineering change orders, or ECOs) can have a disproportionate effect on tapeout schedules, due to the complexity of replacing fill. If not handled effectively, the impacts on file size, run time, and timing closure can significantly extend the tapeout process. In this paper, the authors examine changes to design flow methodology, supported by new fill technology, that enable efficient, fast, and accurate adjustments to metal fill late in the design process. We present an ECO fill methodology coupled with the support of advanced fill tools that can quickly locate the portion of the design affected by the change, remove and replace only the fill in that area, while maintaining the fill hierarchy. This new fill approach effectively reduces run time, contains fill file size, minimizes timing impact, and minimizes mask costs due to ECO-driven fill changes, all of which are critical factors to ensuring time-to-market schedules are maintained.

In this paper, we propose a fast layout decomposition algorithm in litho-etch-litho-etch (LELE) type double patterning considering the yield. Our proposed algorithm extracts stitch candidates properly from complex layouts including various patterns, line widths and pitches. The planarity of the conflict graph and independence of stitch-candidates are utilized to obtain a layout decomposition with minimum cost efficiently for higher yield. The validity of our proposed algorithm is confirmed by using benchmark layout patterns used in literatures as well as layout patterns generated to fit the target manufacturing technologies as much as possible. In our experiments, our proposed algorithm is 7.7 times faster than an existing method on average.

In this paper, a generalized model to predict fin-width roughness (FWR) induced FinFET device variability is developed using the boundary perturbation method. An analytic solution to Poisson’s equation with a perturbed boundary is derived to describe the FWR effects on the sub-threshold electric potential and drain current. High model accuracy under various device operating conditions is demonstrated by a detailed comparison with TCAD simulations. The correlation among the threshold-voltage shift, dominant fin-roughness frequency, and phase difference (between two dominant fin-edge roughness functions) is identified. It is found that a periodic fluctuation of the threshold voltage can be induced by the phase difference, while more significant variations are observed at lower frequencies. Our study also shows that thinner gate oxide and wider fins will help to reduce the FWR effects.

Litho-Etch-Litho-Etch (LELE) type double patterning technology (DPT) is known to have an advantage of layout flexibility. However, there are two problems when a hotspot, which is not fixable by tuning OPC, is detected. One is repeating a data preparation flow including decomposition, OPC, and verification by lithography simulation is quite time consuming. The other is a risk to introduce new hotspots at different locations. In this report, a new method to fix hotspots with layout modification of limited area will be presented. The proposed method can reduce not only turnaround time to fix a hotspot but also the number of iterations since it prevents generation of hotspots at new locations.

Decomposition-aware layout design improvements for 8, 9, 11, and 13-track 20/14nm standard cells are presented. Using a decomposition-aware scoring methodology that quantifies the manufacturability of layouts, the Double Patterning Technology (DPT)-compliant layouts are optimized for DPT-specific metrics that include: the density difference between the two decomposition mask layers, the enclosure of stitching areas, the density of stitches, and the design regularity of stitching areas. For a 9-track standard cell, eliminating the stitches from the layout design improved the composite score from 0.53 to 0.70.

In this paper, we present the approach and results of resist profile aware source mask optimization (SMO). In this approach, the cost functions for optimization include the image properties calculated not only from the resist bottom image planes, but also from the top image planes. Consequently, the optimized source and mask shapes are a good balance between the process window for the bottom CD’s, and top CD control to ensure a straight resist profile favorable for the etching process. We built up the flow of resist profile aware SMO and implemented it on a 1× nm node back-end layer. Two best candidate sources, SMO1 and SMO2 were generated from the conventional SMO flow and the resist profile aware SMO flow, respectively. The simulation results indicate that a better resist profile is achieved by SMO2, although it gives rise to a relatively smaller overlapping process window evaluated at the resist bottom. Wafer data including bottom CD measurement for critical pattern clips and cross-sectional SEM images from selected patterns have shown good matching with the simulation results, indicating that resist-profile aware SMO is a feasible approach to optimize the illumination sources for a reasonable bottom CD based process window as well as favorable resist profiles.

In previous work¹, we introduced a new technology called Flexible Mask Optimization (FMO) that was successfully used for localized OPC correction. OPC/RET techniques such as model-based assist feature and process-window-based OPC solvers have become essential for addressing critical patterning issues at 2× and lower technology nodes. With an FMO flow, critical patterns were identified, classified and corrected in localized areas only, using advanced techniques. One challenge with this flow is that once the hotspots are identified, a user still has to come up with OPC solutions to address the hotspots. This process can be cumbersome and time consuming as different types of hotspots with new designs may require different recipes, causing delays to tapeout. What is required is a robust, powerful and automated OPC technique that can handle various types of hotspots, so an automatic hotspot correction flow can be established. In this work, we introduce a new cost-function-based OPC technique called Co-optimization OPC that can be used to correct various types of hotspots with minimum tuning effort. In this approach, the OPC solver simultaneously solves for all the segments in a patch including main and sub-resolution assist features (SRAF), applying additional user-defined cost function constraints such as MEEF, PV band, MRC and SRAF printability. Unlike conventional OPC solvers, Cooptimization solvers can also move and grow SRAFs, which further improves the process window. The key benefit of the Co-optimization OPC solution is that it can be used in a standard recipe to resolve many different hotspots encountered across various designs for a given layer. In this study, we demonstrate that Co-optimization OPC can be successfully used to address various types of hotspots across designs for selected 2× nm node line/space layers, as an example. These layers have been particularly challenging as they use single-exposure lithography with k1 around 0.3. Aggressive RET solutions are required to address the patterning challenges for this layer. Finally, we will report on implementation of the Co-Optimization OPC Recipe within the FMO framework for hotspot correction.

Self-aligned multiple patterning (SAMP) is a promising technology to scale IC devices to 7-nm half pitch and several 3- mask negative-tone SAMP processes for 2-D BEOL patterning applications have been proposed recently. In this paper, the existing coloring rules in self-aligned quadruple and sextuple patterning (SAQP and SASP) processes are reexamined first. We further discuss the geometric relation between various features and remove the unnecessary constraints, and develop improved layout decomposition algorithms for both processes. The cut-mask related overlay issue is addressed by proposing an edge-expansion solution when generating the cut patterns. Finally, we show that numerous standard M1 cells in the Open Cell Library, when slightly modified, can be successfully decomposed. This verifies the functionality of the new decomposition algorithms for continuous logic scaling to deep nano-scale using SAMP techniques.

In this paper we study the importance of accurate model-based simulation on characterization of the integrated circuit performance. We analyze device sensitivity to process variability and its impact on circuit timing. We show that only a small fraction of devices whose characteristics are significantly affected by process variability actually have correspondingly significant effect on the overall circuit performance. We suggest several ways to use this observation to improve robustness of circuits. We see that a significant fraction of devices is affected by the layout context and should be considered sensitive. However, and it is especially true in large designs, only a small fraction of these devices is critical for the circuit performance. Obviously, to make the design more robust we have to avoid devices which are both sensitive and critical

CMP effects on manufacturability are becoming more prominent as we move towards advanced process nodes, 28nm and below. It is well known that dishing and erosion occur during CMP process, and they strongly depend on pattern density, line spacing and line width ^[1]. Excessive thickness or topography variations can lead to shrinkage of process windows, causing potential yield problems such as resist lifting or printability issues. When critical patterns fall into regions with extreme topography variations, they would be more sensitive to defects and could potentially become yield limiters or killers. Scanner tools compensate and correct topography variations by following the given profile ^[2]. However the scanner exposure window size is wider compared to local topography variations in design. This difference would generate new lithography focus sensitive weak points which may be missed. Experiments have been conducted as shown in Fig 1. Design under manufacturing has been subjected to scanner tool topography focus corrections. Despite of the corrections, Site B topography height has worsened while site A and C shown some improvements. As a result, additional improvements need to be done to meet manufacturability requirements.