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Hardware architecture for projective model calculation and false match refining using random sample consensus algorithm

[+] Author Affiliations
Ehsan Azimi

Islamic Azad University, Department of Computer Engineering, Science and Research Branch, Daneshgah Boulevard, Simon Bulivar Boulevard, Tehran, Iran

Alireza Behrad, Mohammad Bagher Ghaznavi-Ghoushchi

Shahed University, Department of Electrical Engineering, Tehran Qom Expressway, Tehran, Iran

Jamshid Shanbehzadeh

Kharazmi University, Department of Computer Engineering, Faculty of Engineering, Khaghani Street, Tehran, Iran

J. Electron. Imaging. 25(6), 063014 (Dec 05, 2016). doi:10.1117/1.JEI.25.6.063014
History: Received July 12, 2016; Accepted November 14, 2016
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Abstract.  The projective model is an important mapping function for the calculation of global transformation between two images. However, its hardware implementation is challenging because of a large number of coefficients with different required precisions for fixed point representation. A VLSI hardware architecture is proposed for the calculation of a global projective model between input and reference images and refining false matches using random sample consensus (RANSAC) algorithm. To make the hardware implementation feasible, it is proved that the calculation of the projective model can be divided into four submodels comprising two translations, an affine model and a simpler projective mapping. This approach makes the hardware implementation feasible and considerably reduces the required number of bits for fixed point representation of model coefficients and intermediate variables. The proposed hardware architecture for the calculation of a global projective model using the RANSAC algorithm was implemented using Verilog hardware description language and the functionality of the design was validated through several experiments. The proposed architecture was synthesized by using an application-specific integrated circuit digital design flow utilizing 180-nm CMOS technology as well as a Virtex-6 field programmable gate array. Experimental results confirm the efficiency of the proposed hardware architecture in comparison with software implementation.

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Citation

Ehsan Azimi ; Alireza Behrad ; Mohammad Bagher Ghaznavi-Ghoushchi and Jamshid Shanbehzadeh
"Hardware architecture for projective model calculation and false match refining using random sample consensus algorithm", J. Electron. Imaging. 25(6), 063014 (Dec 05, 2016). ; http://dx.doi.org/10.1117/1.JEI.25.6.063014


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