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Field programmable gate arrays-based number plate binarization and adjustment for automatic number plate recognition systems

[+] Author Affiliations
Xiaojun Zhai

University of Hertfordshire, School of Engineering & Technology, Hatfield, United Kingdom

Faycal Bensaali

University of Hertfordshire, School of Engineering & Technology, Hatfield, United Kingdom

Reza Sotudeh

University of Hertfordshire, School of Engineering & Technology, Hatfield, United Kingdom

J. Electron. Imaging. 22(1), 013009 (Jan 15, 2013). doi:10.1117/1.JEI.22.1.013009
History: Received October 10, 2012; Revised December 16, 2012; Accepted December 21, 2012
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Abstract.  Number plate (NP) binarization and adjustment are important preprocessing stages in automatic number plate recognition (ANPR) systems and are used to link the number plate localization (NPL) and character segmentation stages. Successfully linking these two stages will improve the performance of the entire ANPR system. We present two optimized low-complexity NP binarization and adjustment algorithms. Efficient area/speed architectures based on the proposed algorithms are also presented and have been successfully implemented and tested using the Mentor Graphics RC240 FPGA development board, which together require only 9% of the available on-chip resources of a Virtex-4 FPGA, run with a maximum frequency of 95.8 MHz and are capable of processing one image in 0.07 to 0.17 ms.

© 2013 SPIE and IS&T

Citation

Xiaojun Zhai ; Faycal Bensaali and Reza Sotudeh
"Field programmable gate arrays-based number plate binarization and adjustment for automatic number plate recognition systems", J. Electron. Imaging. 22(1), 013009 (Jan 15, 2013). ; http://dx.doi.org/10.1117/1.JEI.22.1.013009


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