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High-performance very large scale integration architecture design for various-ratio image scaling

[+] Author Affiliations
Chung-chi Lin

National Yunlin University of Science & Technology, Graduate School of Engineering Science and Technology, 123 University Road Section 3, Touliu, Yunlin 640, Taiwan

Ming-Hwa Sheu

National Yunlin University of Science & Technology, Graduate School of Engineering Science and Technology, 123 University Road Section 3, Touliu, Yunlin 640, Taiwan

Huann-Keng Chiang

National Yunlin University of Science & Technology, Graduate School of Engineering Science and Technology, 123 University Road Section 3, Touliu, Yunlin 640, Taiwan

Chishyan Liaw

Tunghai University, Department of Computer Science and Information Engineering, 181 Section 3, Taichung-Kung Road, Taichung 407, Taiwan

J. Electron. Imaging. 17(4), 043010 (November 04, 2008). doi:10.1117/1.3010883
History: Received February 21, 2008; Revised July 31, 2008; Accepted August 31, 2008; Published November 04, 2008
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This paper presents a low-cost and high-speed architecture of bicubic convolution interpolation for high-quality digital image scaling. This architecture reduces the computational complexity of generating weighting coefficients and number of memory access times. Furthermore, it attempts to minimize the error propagation that results from the fraction truncations when calculating pixel coordinates under fixed-point operations. Error propagation significantly diminishes the output image quality for hardware interpolation. In order to avoid the inaccuracy accumulation, a simple periodical compensation technique is presented to improve the average root-mean-square error significantly. From the perspective of hardware cost, the presented architecture has 50% saving compared to the latest bi-cubic hardware design work. Finally, this architecture has been successfully designed and implemented with Taiwan Semiconductor Manufacturing Company (TSMC) 0.13μm complimentary metal oxide semiconductor technology. The simulation results demonstrate that the high-performance architecture of bicubic convolution interpolation at 279MHz with 30643 gates in a 498×498μm chip is able to process various-ratio image scaling for full high-definition display device in real time.

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© 2008 SPIE and IS&T

Citation

Chung-chi Lin ; Ming-Hwa Sheu ; Huann-Keng Chiang and Chishyan Liaw
"High-performance very large scale integration architecture design for various-ratio image scaling", J. Electron. Imaging. 17(4), 043010 (November 04, 2008). ; http://dx.doi.org/10.1117/1.3010883


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