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Cache-optimized implementation of the filtered backprojection algorithm on a digital signal processor

[+] Author Affiliations
Ricardo A. Neri-Calderón

Tecnológico de Monterrey, Campus Monterrey, Center for Electronics and Telecommunications, Av. Eugenio Garza Sada 2501 Sur, CP 64849, Monterrey, NL, México

Sergio Alcaraz-Corona

Tecnológico de Monterrey, Campus Monterrey, Center for Electronics and Telecommunications, Av. Eugenio Garza Sada 2501 Sur, CP 64849, Monterrey, NL, México

Ramón M. Rodríguez-Dagnino

Tecnológico de Monterrey, Campus Monterrey, Center for Electronics and Telecommunications, Av. Eugenio Garza Sada 2501 Sur, CP 64849, Monterrey, NL, México

J. Electron. Imaging. 16(4), 043010 (November 29, 2007). doi:10.1117/1.2815987
History: Received July 09, 2006; Revised June 20, 2007; Accepted June 22, 2007; Published November 29, 2007
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The reconstruction of an image from its projections through filtered backprojection is not new and has gained popularity since its application on computerized tomography (CT) for medical imaging. However, the number of projections to reconstruct a single image can be in the thousands. Thus, significant computational power is required. Today’s digital signal processors (DSPs) offer an alternative for implementations of a backprojector to process large amounts of data. We demonstrate an implementation in a fixed-point DSP. This implementation is optimized for cache memory to reduce CPU stalls, and we achieved up to 99.6% of effective CPU cycles. With a DSP running at 1GHz, an image of 1200×1200 pixels can be reconstructed from 180 projections in 1s.

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© 2007 SPIE and IS&T

Citation

Ricardo A. Neri-Calderón ; Sergio Alcaraz-Corona and Ramón M. Rodríguez-Dagnino
"Cache-optimized implementation of the filtered backprojection algorithm on a digital signal processor", J. Electron. Imaging. 16(4), 043010 (November 29, 2007). ; http://dx.doi.org/10.1117/1.2815987


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