Image and Video Compression

Novel architecture for the JPEG2000 block coder

[+] Author Affiliations
Darren Freeman, Greg Knowles

Flinders University, School of Informatics and Engineering, PO Box 2100, Adelaide 5001, Australia E-mail: gknowles@infoeng.flinders.edu.au

J. Electron. Imaging. 13(4), 897-906 (Oct 01, 2004). doi:10.1117/1.1785802
History: Received May 29, 2003; Revised Dec. 2, 2003; Accepted Feb. 25, 2004; Online September 30, 2004
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JPEG2000 is the newest international standard to be produced by the Joint Photographic Experts Group (JPEG) and it has recently been published as an International Standards Organization/IEC standard and as an ITU-T recommendation. It complements most of the currently used standards including the original JPEG, usually with superior compression for the same image quality, or alternatively with superior image quality for the same bit rate. The algorithm uses the wavelet transform followed by an embedded block coder incorporating the MQ arithmetic coder. In this article we give a novel hardware architecture for the block coder and MQ coder as used in the JPEG2000 standard. Together with appropriate software, this design enables a high performance system-on-chip solution for JPEG2000 image compression. We have included sufficient introductory material to interest readers unfamiliar with either JPEG2000 or hardware design. © 2004 SPIE and IS&T.

© 2004 SPIE and IS&T

Citation

Darren Freeman and Greg Knowles
"Novel architecture for the JPEG2000 block coder", J. Electron. Imaging. 13(4), 897-906 (Oct 01, 2004). ; http://dx.doi.org/10.1117/1.1785802


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